AURIX™ Forum Discussions

[Ptar]

As per 13.3.5.1.6 Reading a Single Memory Location, if I configure the register, I can access single address to read.
But If I give, RAEN= 0, MCi_RANGE.ADDR (Where i = 1 CPU0 DTAG) = 0000000000000b which is of 14bits. Which memory location of DTAG will be accessed? How does 14bits mapped to 32bits address.

[Ptar]

The offset address will be from 0000h to 17ffh, that means 14bits are enough to represent the offset address. right? 0001 0111 1111 1111 -> 1 0111 1111 1111.

As per my understanding, what ever address we give in MCi.ADDR is offset address of CPU0 DTAG RAM when i = 1

[Jeremy_Zhou]

Hi @Ptar ,

1) The offset address will be from 0000h to 17ffh, that means 14bits are enough to represent the offset address. right?

-- Yes, it's right.

Further, I'd like to suggest you refer to the MTU_MBIST demo to implement read values from the DTAG RAM.

BR,

Jeremy

[Ptar]

Hi @Jeremy_Zhou ,

OK. I will check. If we write data to DTAG using single address mode (MC.RANGE = 0X00), the data at mentioned address only will be modified, right?  

I have tried to read the data from DTAG RAM address 700C 0000 and used view-->dump option to view CPU0 DTAG RAM memory.

The data present in the address was 700C 0000: 0000 0000  ???? ????

But when read the 700C 0000 using the RDBFL register, the value is as following.

RDBFL0: 0001
RDBFL1: 0088
RDBFL2:0000
RDBFL3:0011

But these values are not seen while viewing via view->dump -> 700C 0000.

Whether DTAG RAM address is viewable in View-->dump?

[Jeremy_Zhou]

Hi @Ptar ,

Actually, I was wondering if you can illustrates the steps of the above testing, so then I can replicate the phenomenon and it can help me to figure it out.

BR,

Jeremy