Hi Lucas ,
With AURIX™, there cannot be several different interrupts with same priority managed by a same Tricore CPU. So each interrupt will have its own priority level.
To manage several interrupts which should have the same interrupt priority, the solution is to use consecutive values of priority for these group of interrupts and set the priority mask value to the highest value for this group.
Example: There are 4 different interrupts managed by CPU0: IT0, IT1, IT2 and IT3. The request is to have the same priority level for these 4 ITs, for instance equal to '5'.
A solution for this case could be:
Priority of IT0 will be set to '5'
Priority of IT1 will be set to '6'
Priority of IT2 will be set to '7'
Priority of IT3 will be set to '8'
When interrupt IT0 is triggered, priority mask is set to '8'
When interrupt IT1 is triggered, priority mask is set to '8'
When interrupt IT2 is triggered, priority mask is set to '8'
When interrupt IT3 is triggered, priority mask is set to '8'
The instruction BISR is well adapted to manage these priorities: “BISR Mask_Value”
It permits to set the mask value (to value '8' here), enable the interrupt (they are disabled when an interrupt is triggered) and save the low context in CSA.
So, it should be the*second instruction executed in each interrupt vector.
I hope that was helpful
Kind regards
Mr.AURIX™
