Mar 31, 2021
03:46 PM
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Mar 31, 2021
03:46 PM
Hello,
The following thread explains how to inject ECC fault on PFlash on TC2xx: https://www.infineonforums.com/threads/11098-How-to-inject-faults-in-Pflash-of-AURIX%C2%99-TC2xx-mic...
I would like to do the same with TC38x in order to test an ECC reporting function. I don't know witch register to use to read the RCODE.
To do the simple way, I'm running on Core0 (from RAM) and would like to read in PFlash 0 but PFI0_ECCR stay null.
I was able to do this test on TC27x several years ago but I'm stuck with TC38x.
Regards
The following thread explains how to inject ECC fault on PFlash on TC2xx: https://www.infineonforums.com/threads/11098-How-to-inject-faults-in-Pflash-of-AURIX%C2%99-TC2xx-mic...
I would like to do the same with TC38x in order to test an ECC reporting function. I don't know witch register to use to read the RCODE.
To do the simple way, I'm running on Core0 (from RAM) and would like to read in PFlash 0 but PFI0_ECCR stay null.
I was able to do this test on TC27x several years ago but I'm stuck with TC38x.
Regards
- Tags:
- IFX
3 Replies
Apr 01, 2021
12:41 AM
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Apr 01, 2021
12:41 AM
Hi TeeEff,
The register to read instead of ECCRPp.RCODE is PFI_ECCR.RCODE - there is a PFI per CPU, so you want PFI0. This contains the ECC code read with the last pflash read operation.
I'm not 100% sure by your question though, and think that I may be missing something. The PFI0_ECCR will only stay null as stated if the ECC value is all 0, or nothing is read from PFlash (as all 0 is the reset value of the register). Did you mean PFI0_ECCS, which reports any ECC errors?
Cheers,
Darren
The register to read instead of ECCRPp.RCODE is PFI_ECCR.RCODE - there is a PFI per CPU, so you want PFI0. This contains the ECC code read with the last pflash read operation.
I'm not 100% sure by your question though, and think that I may be missing something. The PFI0_ECCR will only stay null as stated if the ECC value is all 0, or nothing is read from PFlash (as all 0 is the reset value of the register). Did you mean PFI0_ECCS, which reports any ECC errors?
Cheers,
Darren
Apr 01, 2021
07:08 AM
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Apr 01, 2021
07:08 AM
Thanks Darren,
With your reply I was more confident and I was able to flip bits to generate some ECC errors.
With the debugger, PFI0_ECCR is only updated when I read the 32th byte. I was thinking it will be updated when reading the first byte.
If I want to write in PF2 from Core0 does reading directly PFI2_ECCR will work ? I don't understand if the sentence "A remote CPU can read these registers by triggering a request on the SRI SIF of the local CPU" . How can I do that ?
Regards
With your reply I was more confident and I was able to flip bits to generate some ECC errors.
With the debugger, PFI0_ECCR is only updated when I read the 32th byte. I was thinking it will be updated when reading the first byte.
If I want to write in PF2 from Core0 does reading directly PFI2_ECCR will work ? I don't understand if the sentence "A remote CPU can read these registers by triggering a request on the SRI SIF of the local CPU" . How can I do that ?
Regards
Apr 01, 2021
08:36 AM
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Apr 01, 2021
08:36 AM
Yes, reading PFI2_ECCR from core0 will work. As the PFlashes are all attached to a CPU, what the sentence means is that the registers of any PFlash can be read by any CPU, and if it is a CPU accessing a PFlash attached to another core, it goes across the bus, and will access the PFlash by going through the SRI bus interface of the CPU attached to it.