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Uma
Level 1
Level 1
5 questions asked 5 sign-ins First reply posted

Dear Team,

Please let us know how to enable system timer interrupt in TC3xx.

If u provide sample code it would be of great help.

 

Thanks and Regards,

Uma

 

 

 

 

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1 Solution
cwunder
Employee
Employee
50 solutions authored 250 sign-ins 25 likes received

There are examples that you can import into ADS. 

Enclosed is a bare metal implementation for ADS where the STM0 CMP0 is used to generate a ostick of 1msec.

Also is a one pager to give an example on how to set up the MSIZE0 and MSTART0 values.

/* The System Timer Frequency is 100 MHz */

#include "Ifx_Types.h"
#include "IfxStm.h"

#define SPRN_INT_CPU0_STM0_STMIR0 1
#define SPRN_INT_CPU0_STM0_STMIR1 0

#define CMP0_COMPARE_VALUE  (0xC35u)
#define MSIZE0              (12u)
#define MSTART0             (5u << 8u)
#define CMP1_COMPARE_VALUE  (0x5F5E1u)
#define MSIZE1              (19u << 16u)
#define MSTART1             (8u << 24u)
#define CMP0_TOS            (0u)
#define CMP1_TOS            (0u)
#define ICR_VALUE           (0x1u)
#define OCS_SUS             (18u << 24u)

volatile uint8 osTick;

/**************************************************************************
Object: Initialization of CPU0 System Timer Peripheral
Parameters: None
Return: Nothing
**************************************************************************/
void STM0_Init(void) {

  /* Stop the STM when the CPU is stopped */
  /* Only if OCDS is enabled write into the OCS register */
  if (MODULE_CBS.OSTATE.B.OEN == 1U)
  {
    STM0_OCS.U = OCS_SUS;
  }

  /* The Periodic interval for STM0 is 0.001 Seconds */
  STM0_CMP0.U = STM0_TIM0.U + CMP0_COMPARE_VALUE;

  /* The Periodic interval for STM1 is 1.00 Seconds */
  STM0_CMP1.U = STM0_TIM0.U + CMP1_COMPARE_VALUE;

  /* STM Compare Match Control Register Value: 0x813050C */
  STM0_CMCON.U = MSTART1 | MSIZE1 | MSTART0 | MSIZE0;

  /* the SRC0 Interrupt serviced by TriCore */
  SRC_STM0SR0.U = TOS_CPU0 | SRE_ON | SPRN_INT_CPU0_STM0_STMIR0;

  /* Configure the Interrupt Control Register of the STM  */
  STM0_ICR.U = ICR_VALUE;
}


/**************************************************************************
Object: Interrupt routine for STM0_SR0
Parameters: None
Return: Nothing
**************************************************************************/
IFX_INTERRUPT(STM0_ISR0, VECTAB0, SPRN_INT_CPU0_STM0_STMIR0);
void STM0_ISR0(void) { 
  /* load compare register for next event */
  STM0_CMP0.U += CMP0_COMPARE_VALUE;
  /*let the system know that an tick event occurred */
  osTick++;
}

 

cwunder_0-1645659857516.png

 

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1 Reply
cwunder
Employee
Employee
50 solutions authored 250 sign-ins 25 likes received

There are examples that you can import into ADS. 

Enclosed is a bare metal implementation for ADS where the STM0 CMP0 is used to generate a ostick of 1msec.

Also is a one pager to give an example on how to set up the MSIZE0 and MSTART0 values.

/* The System Timer Frequency is 100 MHz */

#include "Ifx_Types.h"
#include "IfxStm.h"

#define SPRN_INT_CPU0_STM0_STMIR0 1
#define SPRN_INT_CPU0_STM0_STMIR1 0

#define CMP0_COMPARE_VALUE  (0xC35u)
#define MSIZE0              (12u)
#define MSTART0             (5u << 8u)
#define CMP1_COMPARE_VALUE  (0x5F5E1u)
#define MSIZE1              (19u << 16u)
#define MSTART1             (8u << 24u)
#define CMP0_TOS            (0u)
#define CMP1_TOS            (0u)
#define ICR_VALUE           (0x1u)
#define OCS_SUS             (18u << 24u)

volatile uint8 osTick;

/**************************************************************************
Object: Initialization of CPU0 System Timer Peripheral
Parameters: None
Return: Nothing
**************************************************************************/
void STM0_Init(void) {

  /* Stop the STM when the CPU is stopped */
  /* Only if OCDS is enabled write into the OCS register */
  if (MODULE_CBS.OSTATE.B.OEN == 1U)
  {
    STM0_OCS.U = OCS_SUS;
  }

  /* The Periodic interval for STM0 is 0.001 Seconds */
  STM0_CMP0.U = STM0_TIM0.U + CMP0_COMPARE_VALUE;

  /* The Periodic interval for STM1 is 1.00 Seconds */
  STM0_CMP1.U = STM0_TIM0.U + CMP1_COMPARE_VALUE;

  /* STM Compare Match Control Register Value: 0x813050C */
  STM0_CMCON.U = MSTART1 | MSIZE1 | MSTART0 | MSIZE0;

  /* the SRC0 Interrupt serviced by TriCore */
  SRC_STM0SR0.U = TOS_CPU0 | SRE_ON | SPRN_INT_CPU0_STM0_STMIR0;

  /* Configure the Interrupt Control Register of the STM  */
  STM0_ICR.U = ICR_VALUE;
}


/**************************************************************************
Object: Interrupt routine for STM0_SR0
Parameters: None
Return: Nothing
**************************************************************************/
IFX_INTERRUPT(STM0_ISR0, VECTAB0, SPRN_INT_CPU0_STM0_STMIR0);
void STM0_ISR0(void) { 
  /* load compare register for next event */
  STM0_CMP0.U += CMP0_COMPARE_VALUE;
  /*let the system know that an tick event occurred */
  osTick++;
}

 

cwunder_0-1645659857516.png

 

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