AURIX™ Forum Discussions

[JexJiang]

Hi:

How to erase and read Pflash0 on CPU2 on TC39x MCU, when CPU0 has code to execute (CPU0 will access Pflash0, resulting in Contexmangagementrap)? After testing, it is possible for CPU2 to erase and read Pflash2. The API of erasing and reading has been memcpy into PSPR

[µC_Wrangler · Accepted solution]

The TC3xx doesn't support writing to PFLASH while any bus master is reading from that same physical bank.  That applies to all bus masters: not just CPUs, but also the HSM (if enabled), DMA, and Ethernet.

So, you'll need to ensure that other CPUs are either idle, or executing from RAM.  Make sure you either disable periodic interrupts (STM, GTM, etc.) that might still be occurring, or move both the BIV of other CPUs and the interrupt handlers into RAM.

[JexJiang]

Dear µC_Wrangler:

      Thanks for your reply.