Sep 01, 2021
10:11 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sep 01, 2021
10:11 PM
Hi,
We are using TC397 EVK in our project.
We have multiple images programmed on to PFLASH at their respective address spaces. And all of these images will be executed on Core-0 only and rest of the cores are disabled. While running in one particular image, we would like to restrict the Core from accessing/entering other address spaces/ other images. I have tried enabling Flash write protection using UCB blocks (UCB16 (UCB_PFLASH_ORIG)) register and also tried the option of enabling memory protection using MPU Protection set. But both of them are not seem to be working. Hence, would like to understand whether Flash protection can be enabled on this processor to support our requirement? If yes, Please suggest a way of doing it.
Thanks in advance.
Regards,
Srikanth Vemula.
We are using TC397 EVK in our project.
We have multiple images programmed on to PFLASH at their respective address spaces. And all of these images will be executed on Core-0 only and rest of the cores are disabled. While running in one particular image, we would like to restrict the Core from accessing/entering other address spaces/ other images. I have tried enabling Flash write protection using UCB blocks (UCB16 (UCB_PFLASH_ORIG)) register and also tried the option of enabling memory protection using MPU Protection set. But both of them are not seem to be working. Hence, would like to understand whether Flash protection can be enabled on this processor to support our requirement? If yes, Please suggest a way of doing it.
Thanks in advance.
Regards,
Srikanth Vemula.
Solved! Go to Solution.
- Tags:
- aurix tc39x
- IFX
1 Solution
Sep 03, 2021
12:29 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sep 03, 2021
12:29 AM
Please see TriCore TC1.6.2 core architecture manual Volume 1 chapter 10 Memory Protection System. There is described how you must setup the MPU-
1 Reply
Sep 03, 2021
12:29 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sep 03, 2021
12:29 AM
Please see TriCore TC1.6.2 core architecture manual Volume 1 chapter 10 Memory Protection System. There is described how you must setup the MPU-