How to distinguish the trap is triggered by DFlash ECC error?

[Jamber]

Hi, 

How to distinguish the trap is triggered by DFlash ECC error?

I want to do this: if DFlash ECC error occured,  Trap 4 will be triggered. In Trap handler, distinguish this trap is triggered by DFlash ECC error and ignor this trap, jump to the next instruct. But if it's not triggered by DFlash ECC error, don't do that. 

Best Regards

Jamber

[Di_W]

Hi Jamber,

Please refer to AURIXTC3XX_um_part1_v2.0.pdf  for 6.5 chapter Data Memory Unit(DMU)
For ECC related registers, please refer to HF_ECCR, HF_ECCS, HF_ECCC, HF_ECCW, SF_ECCR, SF_ECCS, SF_ECCC, SF_ECCW

A short brief intro is here.

dw

[MoD]

You don't added the device/family name, I guess TC3xx:

In case of a trap 4 you can check the following CPU register:

CPUx_DEADD (CPUx Data Error Address Register)

DEADD contains trap address information for the Data memory system. The register is updated with trap
information for MEM, ALN, DSE or DAE traps to aid the localisation of faults.

CPUx_DATR (CPUx Data Asynchronous Trap Register)

The DATR contains asynchronous trap information for the data memory system. The register is updated with trap
information for DAE traps to aid the localisation of faults.
The register is updated whenever a valid trap is detected and the register has no bits already set. It is cleared by
a write (independent of data value).
DAE traps are inhibited if the DATR register is non-zero.

CPUx_DSTR (CPUx Data Synchronous Trap Register)

The DSTR contains synchronous trap information for the data memory system. The register is updated with trap
source information to aid the localisation of faults.
The register is updated whenever a valid trap is detected and the register has no bits already set. It is cleared by
a write (independent of data value).

With the Data Error Address Register you can check if the error is in DFlash and after check on DSTR and DATR (dependent of the trap TIN) you can ignore the trap (don't forget to clear DSTR/DATR). 

[Jamber]

Hi, MoD

Thank you so much for your detailed reply letting me know how to distinguish DFlash ECC, but there are still some questions:

[Yes, the chip is TC377.]

1. Whether  Trap4 Tin6(DIE, Data Memory Integrity Error) need to be check. Is it related to DFlash ECC Error?

2.I think if the trap is synchronous, the program should return to the next instruct addressed by A11; and if the trap is asynchronous, it should return to the instruct addressed by A11. Is it right?

3.Some instruct occupy 4Byte and some occupy 2Byte. If I want jump to the next instruct I should know the size of instruct recorded by A11 to get the next instruct address by either +2 or +4. So could you tell me how to know the size of instruct recorded by A11?

Thank you for your reminding  me clear error information otherwise it will be a bug in project, and I'm looking forward to your reply.

Best regards

Jamber

[MoD · Accepted solution]

1. DIE trap can also comes from other source therefore you must check the address to know the error was in DFlash address range.

2. Yes, this is correct.

3. Read 16 bits (only) from the address in A11. Check if bit 0 is set. If set then it was 32 bit instruction, if bit 0 is 0 then it was a 16 bit instruction.