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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

How to know whether SRI Extender is present for any Aurix 2G part number from the User Manual Appendix or datasheet for that part either directly or indirectly?
Some explanation of the SRI Extender will help to determine the access latency.
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Darren_Galpin
Employee
Employee
First solution authored First like received
The SRI extender links two SRI domains, and each domain has its own XBAR, with its own ID register. If you check how many XBAR ID registers you have, anything more than one indicates that you will have a bus extender linking the two.

The bus extender connects the SCI port of one XBAR to the MCI port of another. For reads it acts as a bus bridge, and maintains the connection until the read is returned. For writes, the transaction is posted - this means that as soon as the address phase is received, it transmits this to the other domain, but responds to the source master immediately requesting data. This reduces system latency, but means that if the write transaction encountered an error in the target system, the error cannot be returned to the source master. However, the XBAR in the target system will flag the error with an alarm.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
For Aurix 1G User Manual, I could find the XBAR Register section as shown below.
But I am unable to find similar section for Aurix 2G.
Can you please provide me a snippet/section number for Aurix 2G User Manual where XBAR_SRI info is present?
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Darren_Galpin
Employee
Employee
First solution authored First like received
Please see section 4 - On-Chip System Connectivity (and Bridges) - there is a register chapter where this is stated. The register names no longer have XBAR_ in the naming in the document, which is why a text search won't find them.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
Thank you for the lead.
So, can I say that TC39x device have SRI Extender which TC38x device doesn't have SRI Extender?
Please confirm if my understanding is correct or not.
One snippet from TC39x is shown below:
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Darren_Galpin
Employee
Employee
First solution authored First like received
You are correct.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

Attached below is the Instruction Fetch Latency from PFlash Banks related to SAK-TC387QP
So, for Core 0 to access address range 0x8030_0000 -- 0x8030_FFFF, it will be 6 SRI Clock cycles. [ Bank1 ]
Similarly for Core 1 to access address range 0x8000_0000 -- 0x8000_FFFF, it will be 6 SRI Clock Cycle. [Bank 0]
But for Core 0 to access 0x8000_0000 -- 0x8000_FFFF, it will be 3 SRI Clock Cycle. [Bank 0]
Is the correct understanding as there is no SRI Extender for SAK-TC387QP device.
Please confirm.
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4285.attach

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Darren_Galpin
Employee
Employee
First solution authored First like received
This is correct. PFLASH bank0 is connected to CPU0, so the access is done via the dedicated interface and is faster. When CPU0 access the other flash banks, then it has to go out onto the bus, hence the extra latency. Note that this is independent of there being a bus extender present or not.
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User9635
Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,

Attached is a snippet from TC38x_Addendum about 10MB and 8MB parts.
For TC387QP, it is well understood how the Flash Banks are locally connected to each of the 4 cores. Highlighted with comments in the snippet by me.
For TC387TP with 3 Cores and 8MB Flash, How the Flash Banks are locally connected to 3 available cores is not clear.
Can you please provide me some details about local connections of 8MB Flash TC387TP parts?
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Darren_Galpin
Employee
Employee
First solution authored First like received
That second case is where software over the air is enabled on a full TC38x 10MB case. Both have four cores, and when at 8MB we split it as follows:-
Core 0: 3 MB
Core 1: 1 MB
Core 2: 3 MB
Core 3: 1 MB
The A-image needs to be the same size as the B-image, hence the split given.

For TC387TP, there are three cores, and the flash is split 2x3MB+1x2MB,
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