May 08, 2020
09:58 AM
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May 08, 2020
09:58 AM
Hello Support,
GLOBCFG.SUCAL=1 will trigger start-up calibration for Aurix 2G.
Then what logic should be used to reset the GLOBCFG.SUCAL to zero?
For Aurix 1G VADC, there is a condition to reliably check for Start-Up calibration completion because of presence of CALS [Bit 29] as shown below.
CALS bit is removed in EVADC for Aurix 2G. So, please provide me a reliable method to check for Start-Up Calibration completion in EVADC of Aurix 2G.
Best Regards
GLOBCFG.SUCAL=1 will trigger start-up calibration for Aurix 2G.
Then what logic should be used to reset the GLOBCFG.SUCAL to zero?
For Aurix 1G VADC, there is a condition to reliably check for Start-Up calibration completion because of presence of CALS [Bit 29] as shown below.
CALS bit is removed in EVADC for Aurix 2G. So, please provide me a reliable method to check for Start-Up Calibration completion in EVADC of Aurix 2G.
Best Regards
- Tags:
- IFX
4 Replies
May 08, 2020
11:16 AM
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May 08, 2020
11:16 AM
In TC3xx, check to see if calibration has completed with GxARBCFG.CAL=0, as specified in the SUCAL description.
May 08, 2020
04:11 PM
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May 08, 2020
04:11 PM
Hello Support,
That means within the code, we will have to look for an edge transition from CAL=0 to CAL=1 and then back to CAL=0 for every EVADC Group instead of the easy way to check for a Flag being SET as was done in Aurix 1G.
Is that correct?
I am assuming edge detection of CAL bit within Embedded Real-Time code will involve do-while loop with tight timing constraint.
Please let me know if end user can avoid any way to avoid edge detection of CAL bit as mentioned above by checking some other signature similar to Aurix 1G.
Best Regards
That means within the code, we will have to look for an edge transition from CAL=0 to CAL=1 and then back to CAL=0 for every EVADC Group instead of the easy way to check for a Flag being SET as was done in Aurix 1G.
Is that correct?
I am assuming edge detection of CAL bit within Embedded Real-Time code will involve do-while loop with tight timing constraint.
Please let me know if end user can avoid any way to avoid edge detection of CAL bit as mentioned above by checking some other signature similar to Aurix 1G.
Best Regards
May 08, 2020
04:41 PM
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May 08, 2020
04:41 PM
Hello Support,
Actually CAL bit will be finally be zero or 1 at the end of calibration is not mentioned anywhere within the document as shown below.
May be there is a error in the document as you can see completely opposite statements.
Best Regards
Actually CAL bit will be finally be zero or 1 at the end of calibration is not mentioned anywhere within the document as shown below.
May be there is a error in the document as you can see completely opposite statements.
Best Regards
Apr 28, 2022
02:29 AM
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Apr 28, 2022
02:29 AM
One additional question, what are the condition to be able to activate the startup calibration? how long does it should take after the ANONC set to 1?