AURIX™ Forum Discussions

[User9635]

Hello Support,
For the PMS related Safety Flip-Flop ALM6[5] reaction event handler software will clear which registers within the software so that it can be ready for the next event occurrence?
Please provide some hint so that we know which registers to be cleared by writing values and hence the ALM6[5] related registers are cleared and ready for the next occurrence of Single Event Upset within PMS.
Some snippets of the user manual pages will be helpful.
In essence, we are trying to implement proper process of handling this Alarm Event within the Hardware and Software design.
I am assuming without LVD Reset which means basically external Power Supply Reset is
the only solution here when we don't use internal EVR of the IC.
Please confirm.

Best Regards

[NeMa_4793301]

I recommend simply triggering an LBIST, which will re-initialize all registers (and RAMs) through the internal firmware's Cold Power On Reset path.

EDIT: Yuck, I forgot the PMS registers don't get initialized that way. Hold on while I think of something better.

[NeMa_4793301]

Combining the PMS Safety Flip Flop protected registers in 11.3.1.1 with the "LVD Reset Value" registers listed in 11.3.1.4 (i.e., the ones that are only initialized by a low voltage reset) leads to just two registers that need to be manually initialized in case of a PMS SFF alarm: PMSWCR0 and PMSWCR5.

PMSWCR0.U = 0x001002D0; // reinitialize PMSWCR0 to its default LVD Reset Value, in case it triggered a Safety Flip-Flop error
PMSWCR5.U = 0x00000000; // reinitialize PMSWCR5 to its default LVD Reset Value, in case it triggered a Safety Flip-Flop error