AURIX™ Forum Discussions

[User18151]

Hi AURIX Community,

how do I synchronize operations between CPU cores?

Thanks and regards
Christine


#8042000 19639

[User18237]

Hi Christine,


The TriCore and the AURIX internal buses support atomic (read-modify-write) instructions and transactions.

See Atomic Transfers in the User Manual, and application note AP32350: AURIX Multi-Core Software Development.

Atomic instructions are generally used to implement multi-core primitives such as semaphores and locks/mutexes.

The Interrupt Router also has a Service Request Broadcast feature that can trigger multiple service requests (interrupts) at a time.

However, due to CPU interrupt priorities and Interrupt Router arbitration, SRB interrupts will not trigger at exactly the same time.


Best regards
Mr. AURIX™

[User9635]

Hello Support,
In the source code for AP32350: AURIX Multi-Core Software Development.
I am unable to find DSYNC instruction being used anywhere.
Can you please provide me a completed source code where DSYNC instruction is being used for AP32350?
According to the following Errata Item Hint: "CPU_TC.H019 Semaphore handling for shared memory resources"
DSYNC must be used.
Best Regards