Not applicable
Jan 03, 2017
02:50 PM
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Jan 03, 2017
02:50 PM
In Infineon Aurix TX29x B-Step
32-bit Single-Chip Microcontroller
User's Manual V1.3 2014-12, are General Purpose I/O Ports Base Address(GPIO) in contradiction?
In Chapter 13.3.2, P0n_IOCR0 (n = 0 - 2) matches the base address of (0xF003A010 + n * 0x100) specified in Table 13-3 and Table 13-4.
In Chapter 13.3.2, for Pn_IOCR0 (n = 10-11), base address is (0xF003A610 + n * 0x100) but for these same registers, address in Table 13-3 is specified at 0xF003B000?
Other GPIO Base Addresses in Chapter 13.3.2 are in contradiction as well?
I'm new to Tricore. Is this a mistake in User's Manual?
32-bit Single-Chip Microcontroller
User's Manual V1.3 2014-12, are General Purpose I/O Ports Base Address(GPIO) in contradiction?
In Chapter 13.3.2, P0n_IOCR0 (n = 0 - 2) matches the base address of (0xF003A010 + n * 0x100) specified in Table 13-3 and Table 13-4.
In Chapter 13.3.2, for Pn_IOCR0 (n = 10-11), base address is (0xF003A610 + n * 0x100) but for these same registers, address in Table 13-3 is specified at 0xF003B000?
Other GPIO Base Addresses in Chapter 13.3.2 are in contradiction as well?
I'm new to Tricore. Is this a mistake in User's Manual?
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2 Replies
Jan 03, 2017
06:49 PM
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Jan 03, 2017
06:49 PM
I don't recognized the issue can you more clearly state the contradiction?
Table 13-3 Register Address Space states the Base Address for P10 it is 0xF003B000 that is also P10_OUT. To calculate Pn_IOCR0 (n=10) its address is 0xF003A610 + n * 0x100. So 0xF003A610 + 0xA00 = 0xF003B010, The Pn_IOCR0 is the base address plus offset of 0x10 as listed in Table 13-4 Registers Overview.
Table 13-3 Register Address Space states the Base Address for P10 it is 0xF003B000 that is also P10_OUT. To calculate Pn_IOCR0 (n=10) its address is 0xF003A610 + n * 0x100. So 0xF003A610 + 0xA00 = 0xF003B010, The Pn_IOCR0 is the base address plus offset of 0x10 as listed in Table 13-4 Registers Overview.
Not applicable
Jan 04, 2017
07:48 AM
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Jan 04, 2017
07:48 AM
There is no contradiction. I was calculating Pn_IOCR0 address incorrectly. Thank you for correcting me.