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Ptar
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Using single wdg at driver level and 2 wdgm instance at service layer level also can monitor both CPU0 and CPU1, right?

Then why different watchdogs are available in TC3XX family ? Is it due to any safety mechanism?

Whether using single wdg (CPU0WDG) can make any safety violation?

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Yuva
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Hello,

In the TC3xx concept, the CPU watchdog is associated with the CPU, the watchdog configuration registers like WDTCPUyCON0 can be written by the specific CPU, CEy register is associated with a specific CPU watchdog.

Thanks.

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Aiswarya_A
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Hello,
Is this query related to MCAL?
MCAL topics cannot be discussed in community.

Regards,
Aiswarya.

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Ptar
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no it is not regarding MCAL. Its regarding TC3xx user manual information regarding Watchdog.

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Yuva
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250 replies posted 250 sign-ins 100 solutions authored

Hello,

In the TC3xx concept, the CPU watchdog is associated with the CPU, the watchdog configuration registers like WDTCPUyCON0 can be written by the specific CPU, CEy register is associated with a specific CPU watchdog.

Thanks.

Ptar
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Hi @Yuva /  @Aiswarya_A ,

if we are not using CPU1/2/3 watchdog timer, but uses ENDINIT timer, then how does end init error can be handled? Using ALM8[11/12/13], reset is initiated?

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Yuva
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250 replies posted 250 sign-ins 100 solutions authored

Hello,

Even when the watchdog is disabled, the endinit functionality needs to be taken care i.e. if you have cleared the endinit bit of these timers, you need to set it back before the timeout. If you are not clearing endinit with CPU1/2/3 watchdog timers, then the alarm is not expected if not serviced assuming the timers are disabled.

Thanks.