Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

AURIX™ Forum Discussions

sowmyapandala
Level 1
Level 1
First reply posted 5 sign-ins First question asked

For flash wait state configuration, if the order of configuration changes , Such as a setting clock frequency first and loading HF_PWAIT and HF_DWAIT values later or loading HF_PWAIT register first , then clock and HF_DWAIT, will it have any effect on functionality. What will be the impact and what is the expected behavior if we change the order? Will it holds same irrespective of the controllers?

The expected and the workaround is not mentioned in the errata sheet. Could you please answer to this query?

 
 

FLASH_TC.H021 - Flash Wait State configuration:

When increasing the SRI and FSI clock frequencies: first set registers
HF_PWAIT and HF_DWAIT to the correct values, and then change the clock
configuration.
When decreasing the SRI and FSI clock frequencies: first change the clock
configuration, and then set registers HF_PWAIT and HF_DWAIT to the correct
values.

 

0 Likes
1 Solution
µC_Wrangler
Employee
Employee
25 likes received 25 solutions authored First like given

Hi sowmyapandala.  If you increase the clock frequency first, and the number of wait states in HF_PWAIT is too small for the faster clock speed, then there may be an uncorrectable PFLASH read error as the next instructions are executed.

The same applies to an out-of-order sequence when decreasing clock speed: do not set HF_PWAIT and HF_DWAIT to smaller values before decreasing the clock speed.

View solution in original post

0 Likes
3 Replies
µC_Wrangler
Employee
Employee
25 likes received 25 solutions authored First like given

Hi sowmyapandala.  If you increase the clock frequency first, and the number of wait states in HF_PWAIT is too small for the faster clock speed, then there may be an uncorrectable PFLASH read error as the next instructions are executed.

The same applies to an out-of-order sequence when decreasing clock speed: do not set HF_PWAIT and HF_DWAIT to smaller values before decreasing the clock speed.

0 Likes
sowmyapandala
Level 1
Level 1
First reply posted 5 sign-ins First question asked

Hello, I have some more queries.

Is the default or the last configured wait state is considered instead of the one we would like to set or some other value. (will be updated with the new wait state in register?)
And other question is ,In our application, we configured first PWAIT ,clock and then DWAIT. Do we have any issue if we follow this order?
Also Do we get any issues if we access memory before changing wait state?

0 Likes
µC_Wrangler
Employee
Employee
25 likes received 25 solutions authored First like given

Hi Sowmya.  The order of setting HF_PWAIT and HF_DWAIT doesn't matter.

You can absolutely encounter errors if you access memory with incorrect wait states.

0 Likes