Ethernet Link Status

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pistons7
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The "low_level_init" function is called when lwip is initialized, and it is determined whether LNKSTS of "GETH_MAC_PHYIF_CONTROL_STATUS" is 1.

But this "GETH_MAC_PHYIF_CONTROL_STATUS" in the user documentation
It says "This register is optional. It is present only when the MAC is configured for the SGMII, RGMII, or SMII PHY interface."

Therefore, when using the CPU side as MII and the Ethernet IC side as RvMII, I think that LNKSTS cannot be determined.
How should I check the link status in case of MII/RvMII combination?

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1 Solution
Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hello,

There are two methods to configure the PHY.

The first method is to configure the PHY using the Management Data Input/Output interface (MDIO). MDIO is implemented by two signals:

  • MDIO Interface Clock (MDC): clock driven by the MAC device to the PHY.
  • MDIO data: bidirectional, the PHY drives it to provide register data at the end of a read operation.

In order for the MAC to be able to communicate with the PHY, the hardware address of the PHY must be known. Please refer to your PHY’s datasheet regarding finding out its physical address.

Just like I2C, the MDIO interface is open drain so internal/external pull up resistors are required based on the desired speed of the interface.

The MDIO connection between the MAC and the PHY can be check with functions such as:

 

  • READ FUNCTION

 ** 

void IfxGeth_phy_Clause22_readMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 *pData)

{

    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Read, Busy

    GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 8)| (3 << 2) | (1 << 0);

 

    IFXGETH_PHY_WAIT_GMII_READY();

 

    // get data

    *pData = GETH_MAC_MDIO_DATA.U;

}

 

  • WRITE FUNCTION

void IfxGeth_Phy_Clause22_writeMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 data)

{

    // put data

    GETH_MAC_MDIO_DATA.U = data;

 

    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Write, Busy

    GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 8)| (1 << 2) | (1 << 0);

 

    IFXGETH_PHY_WAIT_GMII_READY();

}

 

Both functions can be found at /Imported AURIX Project in ADS/Libraries/iLLD/TC3x/Tricore/Geth/Std/IfxGeth.c

The second method to configure the PHY is directly via the media-independent interface between the MAC and the PHY. This kind of configuration is available only for fast media-independent interfaces such as RGMII, SGMII and SMII since the MAC is not physically connected to the PHY via MDIO.

In this situation, the register MAC_PHYIF_CONTROL_STATUS gives us the information about the Link Status bit (LNKSTS).

 

Kind Regards,
Aiswarya.

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hello, 

Could you please provide more information on the software used to determine the link status ?

Kind Regards,
Aiswarya.

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"netif.c" in "\Libraries\Ethernet\lwip\port\src" of "Ethernet_1_KIT_TC397_TFT".

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hello, 

Please use functions out of the iLLDs to read the connected PHY register. The available functions inside IfxGeth.c are:

 

/** \brief Reads a MDIO register of Clause 22 PHY
 * \param layerAddr Layer Address
 * \param regAddr Register Address
 * \param pData Pointer to Data
 * \return None
 */
IFX_EXTERN void IfxGeth_phy_Clause22_readMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 *pData);

/** \brief Writes to a MDIO register of Clause 22 PHY
 * \param layerAddr Layer Address
 * \param regAddr Register Address
 * \param data Data
 * \return None
 */
IFX_EXTERN void IfxGeth_Phy_Clause22_writeMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 data);

/** \brief Reads a MDIO register of Clause 45 PHY
 * \param layerAddr Layer Address
 * \param deviceAddr Device Address
 * \param regAddr Register Address
 * \param pData Pointer to Data
 * \return None
 */
IFX_EXTERN void IfxGeth_phy_Clause45_readMDIORegister(uint32 layerAddr, uint32 deviceAddr, uint32 regAddr, uint32 *pData);

/** \brief Writes to a MDIO register for Clause 45 PHY
 * \param layerAddr Layer Address
 * \param deviceAddr Device Address
 * \param regAddr Register Address
 * \param data Data
 * \return None
 */
IFX_EXTERN void IfxGeth_Phy_Clause45_writeMDIORegister(uint32 layerAddr, uint32 deviceAddr, uint32 regAddr, uint32 data);

/** \brief Sets the maximum size of the packet
 * \param gethSFR Pointer to GETH register base address
 * \param maxPacketSize Minimum size of the frame beyond which giant packet status is set.
 * \return None
 */

Note : In general the MDIO interface is used to detect the Link status of the external PHY. There is not link status on MII/RMII itself.

 

Kind Regards,
Aiswarya.

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Aiswarya_A
Moderator
Moderator
Moderator
25 likes received 250 sign-ins 50 solutions authored

Hello,

There are two methods to configure the PHY.

The first method is to configure the PHY using the Management Data Input/Output interface (MDIO). MDIO is implemented by two signals:

  • MDIO Interface Clock (MDC): clock driven by the MAC device to the PHY.
  • MDIO data: bidirectional, the PHY drives it to provide register data at the end of a read operation.

In order for the MAC to be able to communicate with the PHY, the hardware address of the PHY must be known. Please refer to your PHY’s datasheet regarding finding out its physical address.

Just like I2C, the MDIO interface is open drain so internal/external pull up resistors are required based on the desired speed of the interface.

The MDIO connection between the MAC and the PHY can be check with functions such as:

 

  • READ FUNCTION

 ** 

void IfxGeth_phy_Clause22_readMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 *pData)

{

    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Read, Busy

    GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 8)| (3 << 2) | (1 << 0);

 

    IFXGETH_PHY_WAIT_GMII_READY();

 

    // get data

    *pData = GETH_MAC_MDIO_DATA.U;

}

 

  • WRITE FUNCTION

void IfxGeth_Phy_Clause22_writeMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 data)

{

    // put data

    GETH_MAC_MDIO_DATA.U = data;

 

    // 5bit Physical Layer Adddress, 5bit GMII Regnr, 4bit csrclock divider, Write, Busy

    GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 8)| (1 << 2) | (1 << 0);

 

    IFXGETH_PHY_WAIT_GMII_READY();

}

 

Both functions can be found at /Imported AURIX Project in ADS/Libraries/iLLD/TC3x/Tricore/Geth/Std/IfxGeth.c

The second method to configure the PHY is directly via the media-independent interface between the MAC and the PHY. This kind of configuration is available only for fast media-independent interfaces such as RGMII, SGMII and SMII since the MAC is not physically connected to the PHY via MDIO.

In this situation, the register MAC_PHYIF_CONTROL_STATUS gives us the information about the Link Status bit (LNKSTS).

 

Kind Regards,
Aiswarya.

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