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Hi infineon

As the title said, I got a problem with "Vddk", I use the next formula to configure "Vddk", but some products(not all, same program) will exceed the threshold(±2%) when ambient temperature increasing, and the calculated value close to low boundary? Could you give me some advise? Thanks

Solved! Go to Solution.

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Hi, we try it, but also error, we calculate Act voltage(8 times average) and Ref voltage(also average), still error. We plan to change the deviation to 5%

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ok~I notice, but EDSADC and EVADC, are these two same? I can not find any information of "Vddk" in chapter 33.4.7.

On the other hand, according to 32.12.5, VDDKC and DVDDK( used for calculate Vddk) stored in UCB, we just read it, how can us calibrate?

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Hi @钱女有 ,

EDSADC and EVADC, are these two same?

They are not the same, sorry for my misunderstanding,

The VDDKC and DVDDK parameters obtained during production and stored in the on-chip Flash, this mean that their values cannot be changed.

The EVADC Vddk deviation (dVddk) is specified as -+2% for 5V Vddm and Varef.

However, when we measure Vddk value we have to additionally consider TUE and ENRMS nose inaccuracies of the EVADC itself.

The EVADC inaccuracy due to TUE and ENRMS (x3 sigma) is calculated as follows:

4LSB + 1LSB * 3 = 7LSB = -+8.4mV.

Additionally, in order to address corner cases we have to include the inaccuracy of

the DTS temperature sensor of -+4 degrees when we calculate Vddk Reference value.

The inaccuracy due to DTS is calculated as follows:

-+ (DVDDK * 4), for DVDDK = 0x14C = 332 uV/K, the deviation is -+( 332 * 4 ) = -+1.32mV.

Thus, the total additional deviation we have to account for is a sum of -+8.4mV and -+1.32mV which is -+9.72mV.

The min/max threshold boundary calculation in SW should be extended by this additional deviation.

In the worst case (when DVDDK = 500uV/K + TUE + ENRMS) the total additional deviation is about 1% of Vddk.

Thus, we can advise specifying the absolute Vddk deviation as +-3%.

BR,

Ulises

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Thank you very much, actually we set deviation +-3% to do same test(after +-2% fail), but also fail, and we notice the actual "vddk" deceasing as the temperature increasing, I know that means the parameter DVDDK is negative value, but all our failed products have the same problem. Is there have some reason to cause this? We now have to expand range to +-5%, is OK? By the way, we used alias feature to select CH29(from CH0), will this have an impact？

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Hi @钱女有 ,

Can you share the device that you are using to see if there are some documented information about this problem?

BR,

Ulises

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TC364DP64F300FAAKXUMA1, this name.

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Hi @钱女有

Are you using a reference voltage range below 4.5V ( (V_AREF - V_AGND) <= 4.5 V), in that case you can find in the AURIX™ TC36x Errata Sheet , the following note about a modification of the ADC accuracy parameters:

This mean that in that condition threshold is also increased, and can be another possible reason of the deviation increment.

BR,

Ulises

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Actually we use 5V as reference voltage, come from TLF35584, it provide a independent reference voltage

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Hi @钱女有

Can you provide the information of your measurements:

-Temperature values measured

-Calculations of expected V_DDK

-V_DDK results

BR,

Ulises

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Sorry for late, explain:

Bandgapvoltage means expected VDDK value

Lowboundary/Upperboundary Voltage means expected range(3% deviation)

VrefAct means calculated VDDK result

PcbTemp_degC means temperature

As you can see, the act VDDK very close the lower boundary(not only this chip), and it will exceed low boundary as the 80degC(and above).

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HI @钱女有

For calculating your Bandgapvoltage that is the expected VDDK value are you using your measured temperature or the result of the internal die temperature sensor?

For this case the expected VDDK value should be based in the result of the internal die temperature provided by the register DTSSTAT.RESULT and then this value converted to °C through the equation:

T_J(°C)=[RESULT/G_nom]-273.15,

with G_nom=7.505

BR,

Ulises

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Yes, we do this, the PCBTemp in the picture just for other application but not use for VDDK...

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Can we just set deviation +-5% ? How high is the risk ?

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Hi @钱女有

I have reviewed this issue with the expert team and they comment that is possible that the Varef influences the Vddk measurement accuracy in addition to the ADC and DTS inherent accuracies. Ideally, the peak-to-peak ripple on the Varef rail should be estimated and included in the min/max boundary calculation.

To minimize Varef ripple and noise impact and increase the reliability of the Vddk measurements, is recommended to set the sampling time >=1us and to apply averaging over several consecutive Vddk measurements (at least 8 samples).

BR,

Ulises

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ok~ we will try

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Hi, we try it, but also error, we calculate Act voltage(8 times average) and Ref voltage(also average), still error. We plan to change the deviation to 5%