AURIX™ Forum Discussions

[User19626]

Hey,

According to the TC29x user manual, LCLCON1 default/reset value should be 0x80010000 indicating lockstep is enabled. However, when I read the register, I get all 0s.

I tried manually setting BMI[9] to 1 in the BMHD through Infineon Memtool 4.8 and then flashing the device, but I still get all 0s when I read back LCLCON1. Am I missing something? How can I enable CPU1 lockstep?



Thanks,
Sergeh

[MoD]

When you change any bit in the BMHD then you must recalculate the CRC of this BMHD otherwise the BMHD is invalid because the CRC value don't correspond to the new BMI value.

[User19626]

Thanks for the response.

Hmm that makes sense but why are the default CRC values incorrect for both CRChead and CRCrange? Does this mean by default there is no valid BMHD available and user needs to calculate all of this?

[MoD]

CRCrange is only used when you select ABM as boot mode. In all other boot modes the CRCrange value can be any value. When you change anything in the BMHD (in your case the BMI) then always the CRChead must be recalculated because the header was changed.

[User19626]

Got it. Is the original CRChead from the .hex file calculated correctly? In my case, is 0xB864479B accurate? I try calculating the CRC on my own (using online calculators) and end up with a different 32-bit value.

[cwunder]

To calculate the CRC you need to provide all of the data. If you are looking to just enable the lockstep on CPU1 then you could use something like this:

const uint32 BootModeHeader_0[] = { 
  0xA0000020u, /**< \brief 0x000: .stad: User Code start address*/
  0xB3590270u, /**< \brief 0x004: .bmhdid: Boot Mode Header ID (CODE) = B359H*/
  0x00000000u, /**< \brief 0x008: ChkStart */
  0x00000000u, /**< \brief 0x00C: ChkEnd */
  0x00000000u, /**< \brief 0x010: CRCrange */
  0x00000000u, /**< \brief 0x014: !CRCrange */
  0x586DFD2Fu, /**< \brief 0x018: CRChead */
  0xA79202D0u, /**< \brief 0x01C: !CRChead*/
};

[User19626]

Hey, thanks that's actually what I was looking for. I tried the following configurations, including the one you provided, but all of them return LCLCON1: 0x00000000 after boot. Am I doing something wrong?

const uint32 BootModeHeader_0[] = {
0x80000020u, /* STADBM first user code at 0x8000 0020h */ //orig 0x00000000u
0xb3590270u, /* BMI = 0070h BMHDID = B359h */ //orig 0xb3590070u
0x00000000u, /* ChkStart */
0x00000000u, /* ChkEnd */
0x00000000u, /* CRCrange */
0x00000000u, /* !CRCrange */
0xa6bb0355u, /* CRChead */
0x5944fcaau /* !CRChead */
};

const uint32 BootModeHeader_0[] = {
0x00000000u, /* STADBM first user code at 0x8000 0020h */
0xb3590270u, /* BMI = 0070h BMHDID = B359h */ //0xb3590070u
0x00000000u, /* ChkStart */
0x00000000u, /* ChkEnd */
0x00000000u, /* CRCrange */
0x00000000u, /* !CRCrange */
0x7ccad3e7u, /* CRChead */
0x83352c18u /* !CRChead */
};

[cwunder]

These registers are only initialized by a cold power-on reset (meaning you must remove power then reapply). Did you do this after you programmed the pflash?

[User19626]

Issue resolved.

I had not, I was simply pressing the POR button. Appreciate your help.