I am working on TC364DP microcontroller. I want to know what is the difference between gating signal and triggering signal in EVADC? I have gone through User manual but could not find specific information. Do I need to configure both for EVADC Hw trigger or can I choose between these two?
as the name implies the "Gate" open and closes, this controls the time in which you would like to sample a signal, for example let say you are interested in the first 10ms of a signal, so you program the gate to open every 10ms, when the gate is open, you can start taking samples, let's say a sample every 1ms, then you configure the trigger to 1ms.
in other scenarios you simply want to take periodic samples of a signal, in this case you can program the ADC to use the gate as trigger so every time the gate opens, a sample is triggered.