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Simone_Massimin
Level 1
Level 1
First reply posted First like given 5 sign-ins

Good morning community,

I was consulting the TC3xx manual at chapter 32.16 in which electrical models of EVADC is explained (picture attached below). I'm interested in evaluating if the input signal in my application could be affected by a remarkable error.

Let's assume a case specific in where:

Rext = 2.5 kΩ;

Zain = 145.8 kΩ; (Precharge enable, sampling time 100ns, Cains 3.4pF from Datasheet)

Cext = 4.7nF

In chapter is written that to keep Vain voltage change during sampling phase below 1LSB, Cext shall be greater than 2^n*CAINS. Which in my case seems to not be guarantee. (To comply is necessary Cext > 14nF) how can I evaluate the impact of this mismatch?

In the assumption I am trying to sample a 5V signal source, does the sampled value is VAIN=Vsource*Zain/(Rext+Zain)?

In numeric example is correct to assume:

5V expected conversion 4095, real input voltage to ADC 4.916V sampled value 4025?

How do I consider Iavg according to conversion cycle time? 

I hope my post is not confusing and I would be happy about any reply.

Many thanks

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1 Solution
Yuva
Moderator
Moderator
Moderator
250 replies posted 250 sign-ins 100 solutions authored

Hello,

You mentioned the case is not guaranteed, does it mean you don't have Cext or have a lower value of Cext? I see the calculations in the user manual are for the case without Cext.

Thanks

View solution in original post

2 Replies
Yuva
Moderator
Moderator
Moderator
250 replies posted 250 sign-ins 100 solutions authored

Hello,

You mentioned the case is not guaranteed, does it mean you don't have Cext or have a lower value of Cext? I see the calculations in the user manual are for the case without Cext.

Thanks

Hello,

Thanks for the answer, I was not sure that impedance partition was only for the "without Cext scenario".

In my application I have a Cext of 4.7nF which, according to the manual doesn't guarantee a read with error below 1LSB so I have a lower value of Cext.

So how do i should proceed to evaluate the actual value read by ADC in order to evaluate the error?

Regards.

According to your reply I checked more carrefully the manual and found the consideration I was missing in the sentence. "If no external blocking capacitor CExt is used, the input channel sees the series resistance (RExt + ZAIN) during the
sample time. The analog input voltage, therefore, will be VAIN = VS × ZAIN / (RExt + ZAIN)."

Now it's clear for me how to proceed.

Thanks for the support

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