ECCs detection procedure in TC36x DLMU

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SChafik
Level 1
Level 1
First reply posted First question asked Welcome!

Hello,

I'm having some difficulties regarding the procedure to use to detect the presence of ECCs in the DLMU0 and DLMU1 on AURIX TC36x. I can't find clearly in the reference manual which registers to use. Can anyone tell me how can I proceed ?

Thank you in advance. 

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cwunder
Employee
Employee
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Sorry, I am not really clear on your question. For the SRAM ECC on DLMU0/1 you can use the MTU to enable it, then access this SRAM via the SSH (read/write). Then you can examine the MCi_RDBFLy registers to view both the data and ecc bits.

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Hello,
Thank you for the reply. To clarify my request, I am searching for a method to detect the presence of ECCs in the DLMU0/1 not to view the data and ecc bits. on the LMU module on tc29x, this MEMCON.RMWERR flag is set when reading a memory with ECCs present. For the tc36x we are trying to do the same on the DLMU0/1.

My question: is there a flag that is set when reading from the DLMU0/1 with ECCs present?

Thank you in advance for your help.

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