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abcmo123
Level 1
Level 1
25 sign-ins 10 questions asked 5 questions asked

Dear AURIX users,

If I disable DMA in TC234 device, will there still exist the risk that the CPU0 DMI is unintended writen through SRI BUS ?

TC234 is a single processor device, so there dose not exist CPU1 that will unintended write the CPU0 DMI through SRI BUS.

And CPU0 PSPR will not unintended write the CPU0 DMI through SRI BUS, because it is a program RAM.

Therefore, dose I need to implement CPU bus memory mechanism in TC234 device if I disable DMA? 

abcmo123_0-1678942973704.png

 

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1 Solution
Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @abcmo123 
Thank you for your interest in Infineon Semiconductor products and for the opportunity to serve you.
1 If I disable DMA in TC234 device, will there still exist the risk that the CPU0 DMI is unintended written through SRI BUS ?
-- No, the DMA is impossible to access the RAM automatically, especially, since it's already disabled.

2) Dose I need to implement CPU bus memory mechanism in TC234 device if I disable DMA? 
-- In my opinion, it doesn't need to do it.
BR,
Jeremy

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2 Replies
Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @abcmo123 
Thank you for your interest in Infineon Semiconductor products and for the opportunity to serve you.
1 If I disable DMA in TC234 device, will there still exist the risk that the CPU0 DMI is unintended written through SRI BUS ?
-- No, the DMA is impossible to access the RAM automatically, especially, since it's already disabled.

2) Dose I need to implement CPU bus memory mechanism in TC234 device if I disable DMA? 
-- In my opinion, it doesn't need to do it.
BR,
Jeremy

MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored

Addtional modules which can be access DMI are EtherMac in case of TC234 ADAS is used and HSM if available.

If they are no switched on then there is no other module which can access the CPU0 DMI via SRI bus.