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AURIX™ Forum Discussions

User19261
Level 1
Level 1
Hello,

I'm working with the MCU specified in the title.
I need to do some lockstep testing on a project.

I have read the datasheet of the MCU and I seen that this particular MCU is single core yet it has lockstep feature. Up until today I thought lockstep required at least two cores but apparently this is not the case.

This is explained in section 7.4 Lockstep Self Test of the user manual of the CPU.
I have read this but I did not quite understand how it is possible for lockstep feature to exist without at least two cores.
This is what I understand from that section(please correct me where I'm wrong):
Apparently single core lockstep is also possible by having some sort of fault injection mechanism that purposely inserts error in the comparators and checks if faults have been detected.

Please help me understand this by explaining to me how lockstep checking works when there is only one core in a CPU. Thank you
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NeMa_4793301
Level 6
10 solutions authored 5 solutions authored First solution authored
Level 6
In the AURIX architecture, a lockstep CPU is comprised of a master core and a checker core. If Lockstep Mode is not used, the checker core is inactive - it is not possible to use the checker core as an independent CPU.

Lockstep details are described in 6.12.8 Lock Step Implementation in the TC23x User Manual. The checker core duplicates the registers and interfaces (DMI/PMI) of the CPU, but not the memories (DSPR/PSPR/caches).
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User19261
Level 1
Level 1
Hello. So you are saying the MCU is actually dual core but Core0 is used as a checker core with the sole purpose of checking that whatever is running on Core1 is running correctly? Did I understand that right? Thank you for answering!
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NeMa_4793301
Level 6
10 solutions authored 5 solutions authored First solution authored
Level 6
Don't think of it as a dual core - think of it as a single CPU with two paths that execute the same code with a slight delay. That way a soft error is less likely to affect the same thing in both cores simultaneously.

In addition, the master and checker are physically separated on the die, and the checker is an "Anti-Core", where most of the logic is inverted compared to the master core.
User19261
Level 1
Level 1
Thank you for clearing it up for me
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