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abhishek1a
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We need to now the differences between the RAM regions in Aurix.
What is the intended use case, caveats or how Infineon expects them to be used. 
 
Any documentation etc would be helpful.

Data
Scratch-Pad SRAM
Data Cache SRAM
Data Cache TAG SRAM
Program Scratch-Pad SRAM
Program Cache SRAM
Program Cache TAG SRAM
Program Cache SRAM
DLMU
LMU LMURAM
DAM RAM
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µC_Wrangler
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Employee
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Hi Abhishek.  Here's a quick rundown:

Data Scratch-Pad SRAM: Each CPU has its own local memory (DSPR), with 0-wait state access.  Prioritize this for variables used strictly by the local CPU.
 
Program Scratch-Pad SRAM: Each CPU has its own local PSPR, which is optimized for instruction access.  Finding the right linker directives to copy functions into this memory at startup is tricky, but there are some examples.  Consider placing high frequency interrupt code here, the interrupt table itself (BIV), and the trap table (BTV).  It is possible to use this as data RAM instead, but that requires access over the SRI bus, even by the local CPU - so performance is similar to LMU RAM.
 
DLMU - This loosely-coupled memory is still faster for the local CPU.  Prioritize this memory for local variables that didn't fit in DSPR, or for variables written by this core and read by others.
 
LMU LMURAM, DAM RAM - These standalone memories are a bit slower, accessed over the SRI bus.  Put shared data here, but make sure you understand how AURIX data cache works.  Use uncached addressing (segment 0xB) if you don't want to worry about cache coherency.
 
Data Cache SRAM, Data Cache TAG SRAM: These memories are used by the data cache for each CPU.  If you are desperate for more RAM, you can disable DCACHE and use the data cache RAM as regular RAM.
 
Program Cache SRAM, Program Cache TAG SRAM: These memories are used by the program cache for each CPU.  
Program Cache SRAM.  Although it's possible to use PCACHE RAM as regular RAM, that can drastically reduce performance.  Leave PCACHE enabled and let this RAM be.
 
 

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Di_W
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https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Memory_Maps-Training-v01_00-EN.pdf?fileId=5546d46...

Hi abhishek1a,

The access speed and space of memory is the point to consider, even if the use case is not limited and flexible, the specific usage and feasibility generally should be evaluated by the user himself. Above link is for your a quick reference. For details, please refer to below chapters in AURIXTC3XX_um_part1_v2.0.pdf:

2 Memory Maps(MEMMAP)

7 Local Memory Unit(LMU)

8 Default Application Memory(DAM)

 

dw

 

µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

Hi Abhishek.  Here's a quick rundown:

Data Scratch-Pad SRAM: Each CPU has its own local memory (DSPR), with 0-wait state access.  Prioritize this for variables used strictly by the local CPU.
 
Program Scratch-Pad SRAM: Each CPU has its own local PSPR, which is optimized for instruction access.  Finding the right linker directives to copy functions into this memory at startup is tricky, but there are some examples.  Consider placing high frequency interrupt code here, the interrupt table itself (BIV), and the trap table (BTV).  It is possible to use this as data RAM instead, but that requires access over the SRI bus, even by the local CPU - so performance is similar to LMU RAM.
 
DLMU - This loosely-coupled memory is still faster for the local CPU.  Prioritize this memory for local variables that didn't fit in DSPR, or for variables written by this core and read by others.
 
LMU LMURAM, DAM RAM - These standalone memories are a bit slower, accessed over the SRI bus.  Put shared data here, but make sure you understand how AURIX data cache works.  Use uncached addressing (segment 0xB) if you don't want to worry about cache coherency.
 
Data Cache SRAM, Data Cache TAG SRAM: These memories are used by the data cache for each CPU.  If you are desperate for more RAM, you can disable DCACHE and use the data cache RAM as regular RAM.
 
Program Cache SRAM, Program Cache TAG SRAM: These memories are used by the program cache for each CPU.  
Program Cache SRAM.  Although it's possible to use PCACHE RAM as regular RAM, that can drastically reduce performance.  Leave PCACHE enabled and let this RAM be.
 
 
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