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AURIX™ Forum Discussions

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Hello Group,
I work with AURIX TC275_CA step. I write a code in Core1, so that Core1's PSPR/DSPR should be protected, which means Core0 and Core2 should have no write access to it.
DSPR --> 60000000 -- 6001E000
PSPR --> 60100000 -- 60108000

Safety Endinit is Disabled
I define the above Lower and Upper ranges in SPROT_RGNLAx/UAx registers like this:
/*! Setup DSPR Ranges for Protection */
SPROT_RGNLA0.u32 = 0x60000000;
SPROT_RGNUA0.u32 = 0x6001E000;

/*! Setup PSPR Ranges for Protection */
SPROT_RGNLA1.u32 = 0x60100000;
SPROT_RGNUA1.u32 = 0x60108000;

and give access only to Core1 by enabling only CPU1_SAFE (0x08) and CPU1_NON_SAFE(0x04) Tag Id's in RGNACCENAx registers like this

Then enable SafetyEndinit.
But now after this has been executed in Core1, then I try to make a write access to this address 0x60000000 from Core 0, still I am able to write.

Few short questions:
Am I using the write Registers to protect Core's DSPR / PSPR region?
Is there any Global Protection Enable to be done?
What should happen, if after protecting Core1 PSPR/DSPR, a Core 0/2 write access to this address happens, a trap/exception or a SMU alarm?
Thanks in Advance.
1 Reply
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I am also facing same issue.

Did you able to sovle this issue?