Continuous DMA daisy chain for 4 channels

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SivakumarG
Level 1
Level 1
50 sign-ins 25 sign-ins 5 replies posted

Hello team,

Currently i am facing new issue, while configuring DMA with daisy chain for 4 channels.
please find the configuration details

Getting interrupt from EVADC G2CH4 result event and configured DMA Channel 96 for it.
And requirement is to measure 4 EVADC channel details by use of daisy chain method, for that i have configured immediate 3 low priority channels to record the other EVADC channel results.
Following DMA channels are configured as daisy chain to fill 64 x 4 (word) circular buffer
DMA Ch 96 - daisy chain
DMA ch 95 - daisy
DMA ch 94 -daisy
DMA ch 93 - HW trigger

for this above configuration, i only get first two rows of data in circular buffer.
do we need RROAT or TREL to keep TSR.CH bit pending to execute remaining rows of circular buffer ?

And during start of data transfer , i can see the address like

SivakumarG_0-1678299515153.png

 

after 6rows of update or it exceeds 0x300 address, then immediately it goes to 0x200 address

here i need 32 rows to update.

SivakumarG_1-1678299715504.png

 

My configuration is given below for  DMA CH96

SivakumarG_2-1678299836835.png

DMA CH 95

SivakumarG_3-1678299907571.png

 

Could anyone support me to find the solution for this ?

 

 

 

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1 Reply
Giraffe1492
Level 5
Level 5
25 sign-ins 25 likes received 10 solutions authored

Based on the provided information, it seems that the circular buffer is not being filled completely, and the address is being reset after a certain number of rows. This could be due to a few reasons:

  1. The circular buffer size might not be configured correctly. Please ensure that the size of the buffer is appropriate for the number of rows required, and that it is correctly configured in the DMA channel settings.

  2. There might be an issue with the daisy-chain configuration of the DMA channels. Please ensure that the daisy-chain settings are configured correctly, and that the DMA channels are triggered in the correct order.

  3. It's possible that the EVADC channels are not being sampled correctly or consistently. Please ensure that the EVADC channels are configured correctly and that the samples are being triggered at the correct times.

Regarding the question about RROAT or TREL, these settings control the DMA read pointer offset and the trigger event for the DMA channel, respectively. Depending on the requirements of your system, you may need to adjust these settings to ensure that the circular buffer is being filled correctly. However, without more information about the system and the specific requirements, it's difficult to provide more specific advice.

Overall, it might be helpful to review the DMA configuration and the EVADC settings to ensure that they are correctly set up for the system requirements. Additionally, checking the DMA transfer status and any error flags might also provide more information about the issue.

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