Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

AURIX™ Forum Discussions

chadpham75
Level 1
10 sign-ins 5 questions asked 5 replies posted
Level 1

Is there any document explain more about the Configurable Clock Generation Unit for Aurix TC37X device?

I went thru successfully example for GTM_TIM_Capture_1 but I couldn't figure out what is the speed for IFXGTM_CMU_CLKEN_CLK0, and how from the explanation slides is "Enable the CMU clock 0 by calling the function IfxGtm_Cmu_enableClocks()"

I research and there is a link called out the IfxGtm_Cmu_setGclkFrequency(Ifx_GTM *gtm, float32 frequency), but the Expert Tutorial didn't call this function to set the frequency.

I tried to search for the frequency setting up for the GTM module.  

0 Likes
1 Solution
cwunder
Employee
25 likes received 25 solutions authored 100 sign-ins
Employee

There is information in chapter 10 Clocking System that describes the clock sources, PLL's and clock distribution. For the GTM clock is derived as described below (the CCU being referred to is CCUCON0): 

cwunder_0-1659025536868.png

fsource0 could be configured either to fPLL0 (CLKSEL = 01B) or fBACK (CLKSEL = 00B)

View solution in original post

0 Likes
3 Replies
Nambi
Moderator
Moderator 250 sign-ins 100 replies posted 10 likes received
Moderator

Hi,

Aurix 2G Tc3xx uses the GTM IP v3.1.5.1, designed by Bosch. You can find the details of the Configurable Clock Generation Unit in the below GTM specification.

https://www.bosch-semiconductors.com/media/ip_modules/pdf_2/gtm/gtm-ip_specification_v3-1-5-1.pdf

Best Regards.

0 Likes
chadpham75
Level 1
10 sign-ins 5 questions asked 5 replies posted
Level 1

Nambi,

Thank you for the document.  I am actually looking for the top down clock diagram from the xtal input and the map how it become CLS0_CLK.  The document you refer too as the same document from Aurix TC3xx user's manual only show CLS0_CLK as the input for CMU block diagram.  I actually look for more details from the XTAL input itself and how it can be routed and configured.

Thank  you so much for your helps. 

0 Likes
cwunder
Employee
25 likes received 25 solutions authored 100 sign-ins
Employee

There is information in chapter 10 Clocking System that describes the clock sources, PLL's and clock distribution. For the GTM clock is derived as described below (the CCU being referred to is CCUCON0): 

cwunder_0-1659025536868.png

fsource0 could be configured either to fPLL0 (CLKSEL = 01B) or fBACK (CLKSEL = 00B)

0 Likes