Clarification on the Time latency

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nsyed
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Hello,

I am using TC377 in my project, Can you please clarify for Core 0 to read data from DSPR0, DSPR1 & DSPR2 ?
Any reference to the data sheets will be helpful ?

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Yuva
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Hello,

Yes, as Aurix has open memory architecture, core 0 can access DSPR1 and DSPR2 as well but note there will be latency as the access happens through SRI instead of local access. 

Thanks.

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Yuva
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250 replies posted 250 sign-ins 100 solutions authored

Hello,

Yes, as Aurix has open memory architecture, core 0 can access DSPR1 and DSPR2 as well but note there will be latency as the access happens through SRI instead of local access. 

Thanks.

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nsyed
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Hello Yuva, 

Can you please clarify what will be te time penalty/latency if the Core 0 reads data from DSPR1 and DSPR2 vs DSPR0 .

Thanks

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µC_Wrangler
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Check out this table on page 187 of AURIXTC3XX_um_part1_v2.0.pdf:

Table 71 CPU Accesses: Stall cycles for local and SRI resources

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nsyed
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Hello,

Thanks for sharing the information. The cycles listed in Table 71 are fcpux/fsri cycles ?

 

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µC_Wrangler
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The table lists CPU stall cycles.  For most applications, fCPU = fSRI.

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