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Operation001
Level 2
Level 2
First like received First solution authored 10 sign-ins

Greetings,

Im trying to change the memory layout of my board TC397 such that the DLMU locations that are set as:

9000 0000H - 9000 FFFFH 64 Kbyte LMU (CPU0 DLMU)
9001 0000H - 9001 FFFFH 64 Kbyte LMU (CPU1 DLMU)
9002 0000H - 9002 FFFFH 64 Kbyte LMU (CPU2 DLMU)
9003 0000H - 9003 FFFFH 64 Kbyte LMU (CPU3 DLMU)

To

9000 0000H - 9002 FFFFH 192 Kbyte LMU (CPU0 DLMU) (accessible only through CPU0)
9003 0000H - 9003 FFFFH 64 Kbyte LMU (CPU3 DLMU)

I did make the changes in the linker file as-well as the bus access group

Operation001_0-1680601027774.pngOperation001_1-1680601119247.png

Is there something else that I am missing as I haven't been able to get the required results.

Best Regards

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1 Solution

Thanks @Jeremy_Z,

As I understand, to give CPU0 sole access to the CPU1_dlmu and CPU2_dlmu I need to set protection regions through DLMU_SPROT_RGNLAi and DLMU_SPROT_RGNUAi, then set the Access (DLMU_SPROT_RGNACCENAi_W) disabling access from CPU1 &CPU2 through the DMI.

Is it possible for me to set write enable for CPU0 to write on CPU1_dlmu ?

BR,

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5 Replies
Jeremy_Z
Moderator
Moderator
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250 sign-ins 100 likes received 750 replies posted

Hi @Operation001 ,

Did you test on the AURIX Development Studio? And I've no idea the expected result you want, in my opinion, the above memory layout change would bring risk and unpredict issues to the code demo project.

BR,

Jeremly

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Hi @Jeremy_Z ,

Yes I did test this on Aurix development studio. My aim is to combine the memory space under CPU1_dlmu and CPU2_dlmu to CPU0_dlmu and make this accessible only from CPU0. Is there any other way I can achieve this memory allocation apart from the method I have used above?

Thanks and Best regards

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Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @Operation001 ,
Thanks for your reply.
Firstly, the CPU0 is able to access the CPU1_dlmu and CPU2_dlmu, definitely, the cost is taking more clock cycles versus CPU0_dlmu, next, it can't prevent other CPUs to access the dlmus, as it's determined by the core architecture.
Lastly, according to your statement, it seems like you want to store some variables or arrays to the CPU1_dlmu and CPU2_dlmu, which are exclusively used by the CPU0, it's able to make it on software level without modifying the linker file.
BR,
Jeremy

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Thanks @Jeremy_Z,

As I understand, to give CPU0 sole access to the CPU1_dlmu and CPU2_dlmu I need to set protection regions through DLMU_SPROT_RGNLAi and DLMU_SPROT_RGNUAi, then set the Access (DLMU_SPROT_RGNACCENAi_W) disabling access from CPU1 &CPU2 through the DMI.

Is it possible for me to set write enable for CPU0 to write on CPU1_dlmu ?

BR,

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Hi @Operation001 ,

1) Is it possible for me to set write enable for CPU0 to write on CPU1_dlmu ?

-- Yes.

BR,

Jeremy

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