Can the TC387 QSPI read and write without interruptions? Please ask the boss for guidance

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Translation_Bot
Community Manager
Community Manager
Community Manager
 
0 Likes
6 Replies
Translation_Bot
Community Manager
Community Manager
Community Manager

Generally speaking, QSPI's read and write operations can be achieved by polling (polling) rather than interrupting.

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC387-QSPI%E8%83%BD%E5%90%A6%E4%B8%8D%E9%80%9A%E8%BF%87%E4%B8%AD%E6%96%AD%E5%AE%9E%E7%8E%B0%E8%AF%BB%E5%86%99-%E8%B7%AA%E6%B1%82%E5%A4%A7%E4%BD%AC%E6%8C%87%E7%82%B9/m-p/673119

0 Likes
Translation_Bot
Community Manager
Community Manager
Community Manager

I'll check it out and try it out. Meng Xin started doing it. If you don't understand, just ask

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC387-QSPI%E8%83%BD%E5%90%A6%E4%B8%8D%E9%80%9A%E8%BF%87%E4%B8%AD%E6%96%AD%E5%AE%9E%E7%8E%B0%E8%AF%BB%E5%86%99-%E8%B7%AA%E6%B1%82%E5%A4%A7%E4%BD%AC%E6%8C%87%E7%82%B9/m-p/674453

0 Likes
David_R
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes given

Hello @oldsix94  

Yes indeed it's possible, i was working on it, but there are more important things to address so i haven't find the time to finish it, but at least it could help you to start, right now it sends a single data (0xDA) and waits (polling) till the fifo gets empty.

So any question please do not hesitate to send me a pm.

Regards!

IfxQspi_SpiMaster qspi0_M;
IfxQspi_SpiMaster_Channel qspi0_M_Channel;
IfxQspi_SpiMaster_ChannelConfig qspi0_channel;
volatile Ifx_QSPI_SSOC *qspi1_ssoc = &QSPI1_SSOC;

const IfxQspi_SpiMaster_Pins qspi0_pins = {
    &IfxQspi1_SCLK_P10_2_OUT, IfxPort_OutputMode_pushPull,          /* SCLK Pin                       (CLK)     */
    &IfxQspi1_MTSR_P10_3_OUT, IfxPort_OutputMode_pushPull,          /* MasterTransmitSlaveReceive pin (MOSI)    */
    &IfxQspi1_MRSTA_P10_1_IN, IfxPort_InputMode_pullDown,           /* MasterReceiveSlaveTransmit pin (MISO)    */
    IfxPort_PadDriver_cmosAutomotiveSpeed3                          /* Pad driver mode                          */
};

IfxQspi_SpiMaster_Config qspi0 = {
           .qspi = &MODULE_QSPI1,
           .allowSleepMode = FALSE,
           .pauseOnBaudrateSpikeErrors = FALSE,
           .pauseRunTransition = IfxQspi_PauseRunTransition_pause,
           .txFifoMode = IfxQspi_FifoMode_singleMove,
           .txFifoThreshold = IfxQspi_TxFifoInt_1,
           .rxFifoMode = IfxQspi_FifoMode_singleMove,
           .rxFifoThreshold = IfxQspi_RxFifoInt_0,
           .pins = &qspi0_pins,
           .dma.rxDmaChannelId = IfxDma_ChannelId_none,
           .dma.txDmaChannelId = IfxDma_ChannelId_none,
           .dma.useDma = FALSE,
           .base.mode = SpiIf_Mode_master,
           .base.txPriority = 0,
           .base.rxPriority = 0,
           .base.erPriority = 0,
           .base.buffer = NULL_PTR,
           .base.bufferSize = 0,
           .base.isrProvider = IfxSrc_Tos_cpu0,
           .base.maximumBaudrate = 50000000U
   };


static void qspi_channel(void){ //Baudrate & CS pin
    IfxQspi_SpiMaster_initChannelConfig(&qspi0_channel, &qspi0_M);
    qspi0_channel.sls.output.pin = &IfxQspi1_SLSO9_P10_5_OUT;
    qspi0_channel.sls.output.mode = IfxPort_OutputMode_pushPull;
    qspi0_channel.sls.output.driver = IfxPort_PadDriver_cmosAutomotiveSpeed1;
    qspi0_channel.base.baudrate = SPI0_BAUDRATE;
    IfxQspi_SpiMaster_initChannel(&qspi0_M_Channel, &qspi0_channel);
}

extern void qspi_sendandreceive(void){
   volatile Ifx_QSPI_DATAENTRY *spi_tx = &QSPI1_DATAENTRY0;
    uint32 dat = 0xDA;
    //BACON
    qspi0.qspi->BACONENTRY.U = 0x3A71C71; //MSB 8 bits, last = 1
    //CS LOW
    qspi1_ssoc->U = 0x0000FFFF;
    // send new stream
    spi_tx->U = dat;
    // wait until transfer of previous data stream is finished
    while(!qspi0.qspi->STATUS.B.TXF);
    //Clear the TX flag
    qspi0.qspi->FLAGSCLEAR.B.TXC = 1;
    //CS high
    qspi1_ssoc->U = 0x00000000;
}

extern void qspi_ini(void){
 IfxQspi_SpiMaster_initModule(&qspi0_M, &qspi0);
 //Enabling IRQ request flag
 qspi0.qspi->GLOBALCON1.B.TXEN = 1;
 qspi_channel();
}

 

 

Translation_Bot
Community Manager
Community Manager
Community Manager

Thanks so much for your help, I'll try 🤒

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC387-QSPI%E8%83%BD%E5%90%A6%E4%B8%8D%E9%80%9A%E8%BF%87%E4%B8%AD%E6%96%AD%E5%AE%9E%E7%8E%B0%E8%AF%BB%E5%86%99-%E8%B7%AA%E6%B1%82%E5%A4%A7%E4%BD%AC%E6%8C%87%E7%82%B9/m-p/674432

Translation_Bot
Community Manager
Community Manager
Community Manager

 

    // wait until transfer of previous data stream is finished
    while(!qspi0.qspi->STATUS.B.TXF);

 

Can you evaluate the method proposed above for polling to send or receive data from QSPI. However, the interrupt-driven approach is more efficient, as polling may block the CPU.

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC387-QSPI%E8%83%BD%E5%90%A6%E4%B8%8D%E9%80%9A%E8%BF%87%E4%B8%AD%E6%96%AD%E5%AE%9E%E7%8E%B0%E8%AF%BB%E5%86%99-%E8%B7%AA%E6%B1%82%E5%A4%A7%E4%BD%AC%E6%8C%87%E7%82%B9/m-p/674674

David_R
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes given

Update:

The SLSO(CS) channel is missing, so here's the correct config for BACON

 

extern void qspi_sendandreceive(void){
   volatile Ifx_QSPI_DATAENTRY *spi_tx = &QSPI1_DATAENTRY0;
   //BACON
   qspi0.qspi->BACONENTRY.U = 0x93A71C71; //MSB 8 bits last =1 CS = 9
    uint8 dat = 0xDA;
    // send new stream
    spi_tx->U = dat;
    // wait until transfer of previous data stream is finished
    while(!qspi0.qspi->STATUS.B.TXF);
    //Clear the TX flag
    qspi0.qspi->FLAGSCLEAR.B.TXC = 1;
}

 

David_R_0-1705436529429.png

Cheers!

0 Likes