Which address generate the write back error?
There are only two possibilities for write back errors:
Cache line is from flash and modified by software, write back error occurs because you can't write back to flash by this way. Check you software why there is a variable in flash and not in the ram.
The access rights are changed between read the cache line and write back. This can be happen e.g., when during startup a read access to other CPU memory is and this CPU change the rights for the access before the cache line is written back.
I guess you will modify a cache line inside of the flash and get then this error.
Thank you for your replay.
Which register is responsible for the provide the access for cache line write back and read back in the aurix side?
In your case is CPU_DATR bit 9 set (Cache Writeback Error). Check register CPU_DEADD which hold the address where the access don't work.
Thank you for your feedback.
But one observation is some times this issue is bypassing when adding new functions in the software. I think some memory re allocation is bypassing the issue.
This is not bypassed, only the cache writeback don't occur maybe because of other address.
Which address (CPU_DEADD) the error occur?
Now we getting write back error fron 0x80004d31e. But some times we getting the same error from some other functions and some variables. Which are located in the PFlash0 and ram0 respectively.
The address is inside of the flash. It seems that this address is changed in the cacheline which is normally not allowed by this way (flash). Set a write breakpoint to this address then you can see when there is a wrongly store to this address. Now you can check your code, why there is a write to pflash.
Thank you for your support.
I found that some variables are located in the program flash instead of Ram. I moved these variables into ram and working fine. But one doubt previously why this issue is bypassed when adding new functions in the software?
Which cache line will be used is dependent of the address. When you add new functions then issue is not bypassed only the addresses are different and when this cache line is not needed for another variable then there is no write back. Unique solution as you described, move variables into ram.