Bus MPU Safety for Local Memory is for Segment C & D as well as Segment 7 for Core 0

[User9635]

Hello Support,
Shown below is a snippet from Aurix 2G User Manual about Bus MPU Safety Protection.
Does this mean the following?

1> For Core 0, Segment C and Segment 7 are never checked for Bus MPU related to PMI/PSPR Fetch
Similarly for Core 0, Segment D and Segment 7 are never checked for Bus MPU related to DMI/DSPR Data access.
Is that correct?
Or, it is not checked for Segment C and D respectively?
Which one?
Is it only for Local Addressing [Segment C/D] or also for Global Addressing [Segment 7 for Core 0, Segment 6 for Core 1, Segment 5 for Core 2]?
Please elaborate with some example ranges so that I can better understand.


Best Regards

[NeMa_4793301]

Bus MPU Safety Protection only lets a CPU restrict access to its own DSPR and PSPR memories from reads over the SRI bus.

For a CPU accessing its own DSPR and PSPR, it can only restrict data reads from PSPR (not instructions), or restrict instruction reads from DSPR (not data). Both global and local addressing apply.

Figure 51 PMI Block Diagram shows that the CPU has a direct path from the CPU fetch pipeline into its own PSPR. That direct path means that the Bus MPU does not apply.

Figure 52 DMI block diagram show that the CPU has a direct path from the CPU memory pipeline into its own DSPR. That direct path means that the Bus MPU does not apply.

[User9635]

Hello Support,

For the Bus MPU, if the access permission [Write] for other Bus Masters are given in DMI_NON_SAFE Mode, then will the DMI_SAFE mode of the same Bus Master can have access permission [Write] automatically?
I mean does Safe Task has higher privilege and hence if the access is given for Non_Safe Master Tag, Safe Master Tag will automatically have the same access?
Is that correct?
Or there is no automatic privilege inheritance, but it has to match the exact DMI_SAFE or DMI_NON_SAFE Master Tag value to have any access?
Please confirm
Best Regards

[NeMa_4793301]

I don't understand the questions, but let me try to clarify:

Each CPU has two tag IDs for the DMI (data memory interface).

For example: when PSW.S=0, CPU1 uses tag ID 5. When PSW.S=1, CPU1 uses tag ID 6.

There is no automatic inheritance.