Jun 18, 2020
04:13 AM
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Jun 18, 2020
04:13 AM
Hi,
I am using aurix TC233 micro controller.
I want the same function to be executed from multiple core (core 0, 1 and 2).
But the function should execute in parallel, each core should have its own instance of execution (independent local variables etc)
Also the function uses global variable shared across all cores.
How I can do this.
I am using aurix TC233 micro controller.
I want the same function to be executed from multiple core (core 0, 1 and 2).
But the function should execute in parallel, each core should have its own instance of execution (independent local variables etc)
Also the function uses global variable shared across all cores.
How I can do this.
3 Replies
Jun 18, 2020
05:25 AM
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Jun 18, 2020
05:25 AM
The TC233 has only core 0 other core don't exist.
Otherwise you should check the documentation of used compiler how you can use the compiler in a multicore environment.
Otherwise you should check the documentation of used compiler how you can use the compiler in a multicore environment.
Jun 18, 2020
05:27 AM
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Jun 18, 2020
05:27 AM
Well, first... it's important to note that the TC233 only has one core. If you need three cores, consider the TC277 or TC297.
Once you have a CPU with three cores, the rest is relatively simple - any variables declared within the function will be on each CPU's stack, so no conflicts there.
When you say "uses global variable", what does that mean - who updates the variable?
In general, to avoid problems with global variables and the data cache: put global variables in LMU RAM, and change the value of each CPU's PMA0 register from the default value of 0x300 to 0x100, so that LMU RAM is not cached.
Once you have a CPU with three cores, the rest is relatively simple - any variables declared within the function will be on each CPU's stack, so no conflicts there.
When you say "uses global variable", what does that mean - who updates the variable?
In general, to avoid problems with global variables and the data cache: put global variables in LMU RAM, and change the value of each CPU's PMA0 register from the default value of 0x300 to 0x100, so that LMU RAM is not cached.
Dec 01, 2022
08:02 AM
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Dec 01, 2022
08:02 AM
Is there any documentation or tutorial availlable which explains the mentioned steps?
How is it possible to place variables in theLMU RAM?
How is it possible to change the default value of the CPU's PMA0 register?
Thanks and BR,
Florian