AURIX™ Forum Discussions

[MogantiSanjay]

Hi Infineon,

This is sanjay currently working on Tricore 3xx MCU. I had an issue with trap sections. In PFLASH even though Protection is disabled when flashing my application it is going to trap section
What I have done is
1. CPU_FLASHCON1 registers
2.MCAL_CpuEndInitProtReg register.

In traps there are 8 types, Sometimes I am getting Trap 4,Trap 2 etc etc. In D[15] shows 4. After sometimes shows 2 etc etc .

How to reslove the trap issue in Aurix 2G TC3xx.

Thanks in advance

[NeMa_4793301]

Hi Sanjay. The details of each occurrence are important - the trap number and D15 should be captured together to figure out what's going on. Refer to the TriCore Architecture Manual, Chapter 6, Trap System.

Trap 2 is an instruction error, which usually indicates the application has begun executing from an invalid or unprogrammed location. If you view the debugger's callback stack, what instruction is at the Program Counter where the trap occurred?

Trap 4 is generally an address error. It's highly unlikely that D15 would be 4, because there is no Coprocessor Trap on a TC3xx.

[MogantiSanjay]

The trap 4 address location is at 80000160. After my application is flashed it is directly going to trap location. I have crossed verified with the address which I am using

[NeMa_4793301]

What's in D15? Also check DEADD. And list the 4 instructions ending at 0x80000160.

[MogantiSanjay]

D[15] = 4 at one instant. Trap CPU0+x40. 0x80000160.
At this address location contains 0000000 0000000 0000000 0000000.

[NeMa_4793301]

Do you mean the address of the trap handler is at 0x80000160, or that the trap occurred at 0x80000160?

Either way, if the contents of that location are all 0s, that's not valid code. Perhaps you have a problem in linking your application.

[MogantiSanjay]

that the trap occurred at 0x80000160