Aurix TC3xx Safety manual - Clarifying questions

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F_Irlando
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First question asked Welcome!

I would need some clarification about the Aurix TC3xx Safety Manual.

In the paragraph 4.3.1 Introduction, there is the list of safety related function and relevant functional blocks.

For each FB, we are using this table as a reference to understand which HW or SW Safety Mechanism configure or implement to achieve the ASIL level reported in the Safety Related Function Column (e.g. implement/configure NLS-CPU Safety Mechanism to achieve Safey Computation ASIL B).

Our interpretation #1 is that Safety mechanism configuration (SMC) are considered as mandatory initialization and configuration procedures for all ASIL B/C/D provided functional block/functional subblock that are used for the ECU features.  Does anybody agree?

However there are a few safety mechanisms that apparently are not linked to any safety related function or executed by a relevant FB: e.g. ESM[SW]:EMEM.RAM:REG_MONITOR_TEST, ESM[SW]:CIF.RAM:REG_MONITOR_TEST, ESM[HW]:MCU:LBIST_MONITOR, SM[HW]:AGBT:CFG_AS_AP, SM[SW]:FW:MCU_STARTUP_PREOS_FW etc.

Interpretation #2 is that these safety mechanisms are mandatory for each ASIL level (B/C/D) since they allow to achieve SPF and LF metrics as per table reported at page 30. Does anybody agree?

 

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Di_W
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1000 replies posted 250 solutions authored 100 likes received

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Di_W
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1000 replies posted 250 solutions authored 100 likes received

 .

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Di_W
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1000 replies posted 250 solutions authored 100 likes received

Hi,

Please contact your local Infinion representative for Safety questions as it needs NDA issued.

dw

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