AURIX™ Forum Discussions

[User21406]

Hi There,

I am currently trying to execute the interrupt on another core but core0.
https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/GTM_TOM_Interrupt_1_KIT_TC...

According Explanation to the code
https://www.infineon.com/cms/en/product/promopages/aurix-expert-training/
https://www.infineon.com/dgdl/Infineon-AURIX_GTM_TOM_Interrupt_1_KIT_TC397_TFT-Training-v01_00-EN.pd...

Taking the bare example (cutting the LED Stuff) works just fine.

But switching

 timerConfig.base.isrProvider     = IfxSrc_Tos_cpu0

to e.g. cpu1

 timerConfig.base.isrProvider     = IfxSrc_Tos_cpu1

prevents any cpu from servicing this Interrupt.

What I could figure out so far:
The ECC Flag in the SRC_GTMTOM10 is set to 06 when setting the Provider to cpu1.
The ECC Flag in the SRC_GTMTOM10 is set to 00 when setting the Provider to cpu3.
The ECC Flag in the SRC_GTMTOM10 is set to 1C when setting the Provider to cpu0.
The ECC Flag in the SRC_GTMTOM10 is set to 1F when setting the Provider to cpu2. -> There the CPU traps in an error
The ECC Flag in the SRC_GTMTOM10 is set to 19 when setting the Provider to cpu4. -> There the CPU traps in an error
The ECC Flag in the SRC_GTMTOM10 is set to 1A when setting the Provider to cpu5. -> There the CPU traps in an error

For compiling I use gcc.

If there are any questions, please let me know!

BR
Christoph

[NeMa_4793301]

Each CPU has its own BIV register (interrupt vector table) and interrupt enable/disable status (ICR.IE).

Do you have an ISR defined on CPU1? What does CPU1's BIV register with your interrupt offset (SRN * 32 bytes) point to?

Are interrupts enabled on CPU1 (ICR.IE)?

[teoBits]

You can also change the used vector table by changing the second parameter of the macro IFX_INTERRUPT:

/* Macro to define Interrupt Service Routine.
* This macro makes following definitions:
* 1) Define linker section as .intvec_tc_.
* 2) define compiler specific attribute for the interrupt functions.
* 3) define the Interrupt service routine as ISR function.
*
* IFX_INTERRUPT(isr, vectabNum, priority)
* - isr: Name of the ISR function.
* - vectabNum: Vector table number.
* - priority: Interrupt priority. Refer Usage of Interrupt Macro for more details.
*/
IFX_INTERRUPT(interruptGtmTom, 0, ISR_PRIORITY_TOM);

BR,
teoBits

[User21406]

Hi,

thanks very much @UC_wrangler and @teoBits. Both of your answers helped me to figure out, what went wrong. In fact it was the Vector Table Number, I did not set correctly. I did not see the connection between vectabNum and CPU number.
So if anyone else struggles with that:
Core0 -> vectabNum 0
Core1 -> vectabNum 1
Core2 -> vectabNum 2
Core3 -> vectabNum 3
(4 and 5 not checked)

BR,
Christoph