Aurix TC397 MPU error not as expected

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Fitz_
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Recentlly, I'm using AURIX TC397's MPU, 

I config 7 data MPU regions for each cpu(core0 ~ core5), for core4, protection set 0, region 4 is Write enable,

Fitz__0-1678173626559.jpeg

however, when I debug the program, it run into MPW trap, and DEADD register indicate 0x7000521C is violate the MPW 

20230307-152504.jpg

( I'm sure that SYSCON.PROTEN is set and PSW.PRS is set0)

20230307-152749.jpg

My question is:  0x7000521C is between [0x70004BC0, 0x70005290) , why it occur trap 1? does this reasonable?

( ps: this phenomenon also happen in core5 when I debug another time )

 

 

 

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Fitz_
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First solution authored 5 sign-ins First reply posted

thanks,  this problem is solved.

i saw PRS is set0 when trap occur, actually it is Set2 before trap.

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Di_W
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MPE Memory Protection Error : Data access violating memory protection.

First please remove all the protection to try,  then try to focus if Read Error or Write Error.  

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Fitz_
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At the very beginning, the program runs OK, and i think it is a Write Error

Snipaste_2023-03-07_16-06-48.png

i debug by sigle step, when it run st16.b [a15]0x8, d15, it occur trap, and 0x7000521C is a global varible

Snipaste_2023-03-07_16-09-20.png

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Di_W
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Could you please remove the protection? Could you please confirm enabled read and write for protection set 0, region 4?

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Fitz_
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First solution authored 5 sign-ins First reply posted

---1, at the very beginning,  I didn't config any MPU region , and the program runs OK.

---2, i change the region 4 's read permiss to enable, but it seems no difference

Fitz__0-1678178209971.png

 

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Di_W
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Is this code useful? pdf

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Fitz_
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First solution authored 5 sign-ins First reply posted

thanks,  this problem is solved.

i saw PRS is set0 when trap occur, actually it is Set2 before trap.

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