Aurix TC387 - Bus MPU

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cross mob
Level 1
Level 1

I'm currentely working on aurix TC387, and I want to use Bus MPU to seperate cores.
I created a static configuration on which i specify the START and END address and also the Right.

for exampel :

/* CPU3 DSPR/PSPR regions */
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNLA0, BUSMPU_ALL_MEMORY_START }, /* All SRAM access to CPU3 */
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNUA0, BUSMPU_ALL_MEMORY_END },
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNACCENA0_W, BUSMPU_TAGID_CPU3 },

for the moment I just isolate the core( means that this SPR memory region will be dedicated to CORE3.

My question is if for example I want that this core (core3) contains only CAN1 and LIN1 what shall I do ? Is there any document that explains how can we ensure a peripheral access protection ?

Thank you in advance.

1 Reply
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
If you mean that you only want CPU3 to be able to access CAN1 and LIN1, then you'll want to use the access enable registers for those peripherals, to restrict which bus masters have access.

For CAN1 and LIN1, that means CAN1_ACCEN0 and ASCLIN1_ACCEN0.

For which bit to set, you need to know the master tag. Those are listed in Table 86 OnChipBus Master TAG Assignments: the data interface for CPU3 is either 9 (when PSW.S=0) or 10 (when PSW.S=1). But you should also consider whether you actually meant to include CPU3 *and* DMA, since LIN is typically handled with DMA.

So, to restrict CAN1 to just access by CPU3, set CAN1_ACCEN0 = 0x200 (PSW.S=0) or 0x400 (PSW.S=1).

Same for LIN: ASCLIN1_ACCEN0 = 0x200 or 0x400, and maybe add DMA (DMA Resource Parition 0=bit 0, RP1=bit 4, RP2=bit 8, RP3=bit 12).