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alig
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First reply posted First question asked Welcome!

Hello, I was checking interrupt handling but I couldn't understand well. Can you please answer below questions?

 

alig_0-1699452758254.png

User manual says there are 1024 interrupt trigger vector and you can see above there are 1024 Service Request Control Register (SRC), I couldn't find which one is which in reference manual. Is there any table like below which says which number has which interrupt source?
alig_1-1699453089694.png

 

I was examining ASCLIN_Shell_UART_1_KIT_TC375_SB (Aurix Development Studio example) and saw this:

alig_3-1699453763004.png

 

We are giving function address to put vector table with "isr", core that will execute function with "vectabNum", priority with "priority". How hadrware knows which function to execute when new data is received? Because we didn't give any index to that macro so how it knows which index of vector table to put? Thanks.

Ali

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cwunder
Employee
Employee
5 likes given 50 likes received 50 solutions authored

1- How can I find which index of SRC of Interrupt Router for ASCLIN3 RX interrupt?

Each SRN has one unique SRN Index Number within the Interrupt Router module. The index numbers are not required for the functionality of the interrupt router module itself. The index numbers can be used to select a Service Request Nodes for observation via the OTGM feature.

Each device has an appendix that supplies the specific implementation that supplements the family documentation. This is where you will find the specific SRC registers for the device and for the TC375 this is named “TC37x_appx_um_v2.0.pdf”. For the ASCLIN module you can go to is connectivity setting and you will find that each module has three interrupts that connect to the interrupt router.

cwunder_0-1699720993389.png

Now you look up this in these interrupt nodes to find their SRC name and address.

cwunder_1-1699720993425.png

The SRC register holds the SRPN (priority number), TOS (which CPU or DMA handles the event) and the SRE (whether or not the interrupt is enabled). The SRPN level has to match your entry in a vector table when the TOS is a CPU and its vector table.

2- If there is no fixed location in vector table, and I have 2 interrupts which are ASCLIN RX and one ADC end of conversion interrupt. Both have same priority, how core knows which interrupt handle to be executed?

Correct there is no fixed location in a vector table for the SRC this is chosen by you when writing the SCRx.SRPN and SCRx.TOS. This is one of the advantages of the TriCore where you have the freedom to choose the interrupt level priority according to your needs. You cannot have more than one priority for an interrupt in a vector table (i.e. each entry must be unique within a vector table as you can only have one entry from the linker file). If you want all interrupts, to go to one vector this can be done but then you need your own software table to redirect the response. If you need to have the different to be grouped then you can raise the interrupt level to the highest one in your group by using the BISR instruction in your ISR.

cwunder_2-1699720993448.png

With your example for example you want the interrupt priority to be 241 then your code should have something like:

 

 

 

#define SRE_ON    (1u << 10u)  /* Service Request Enable */
#define TOS_CPU0  (0u << 11u) /*TOS is for CPU0*/
#define VECTAB0 0 /*vector table for CPU 0*/
#define SRPN_INT_CPU0_ASCLIN0_TX 241 /* interrupt priority level */

void ASCLIN0_Init(void)
{
  /*your peripheral initialization code*/
  SRC_ASCLIN0TX.U  = TOS_CPU0 | SRE_ON | SRPN_INT_CPU0_ASCLIN0_TX;
}

IFX_INTERRUPT(ASCLIN0_TxISR, VECTAB0, SRPN_INT_CPU0_ASCLIN0_TX);
void ASCLIN0_TxISR(void)
{
 /*your ISR code*/
}

 

 

 

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cwunder
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Employee
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The TC37x_appx_um_v2.0 provides the information as to which SRC registers are available in a TC37x device. You need to write the Service Request Priority Number (SRPN) in the SRC register. This has to match the priority that placed in the vector table for a CPU. The SRC TOS bitfield also needs to match the expected vector table you defined in the IFX_INTERRUPT macro. 

In your example you can look at this function

 

IfxSrc_init(src, tos, config->interrupt.txPriority);

 

 

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alig
Level 1
Level 1
First reply posted First question asked Welcome!

Then I have more questions:

So can we say there is no fixed location in vector table, items ordered according to priority?

Service Request Priority Number (SRPN) can be at most 255, but count of Service Request Control Register (SRC) is 1024 which means SRPN can't be unique. Can 1024 SRC have same SRPN?

 

alig_1-1699518692562.png

alig_0-1699518461958.png

Where can I learn SRC_BCU_SPB offset is 20Hex or XBAR0 offset is 30Hex? Where this information comes from in User Manual?

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cwunder
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Employee
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Correct the interrupt priority is not fixed it only depends on its position in the vector table. The higher the value written to the SPRN the higher the priority when a service provider is a CPU. If the service provider is the DMA then the SRPN value represents the DMA channel number. 

I think you are mixing the number of SRC registers available in the Interrupt router (IR). This has nothing to do with the priority that you define for an interrupt. For example with the ASCLINx there are three possible interrupts that are routed to the IR.

cwunder_0-1699543881897.png

 

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alig
Level 1
Level 1
First reply posted First question asked Welcome!

Actually I was asking 2 different questions. I will explain below. I just started to work on Aurix and TriCore so I thought if I write simple examples bare-metal I can get familiar with Aurix in shorter time, in this way I can have better knowledge how to enable peripherals, how to handle interrupts etc. I was expecting to see "Interrupt Sources Table" in user manual, find the index of my interrupt in that table, lets say ASCLIN3 RX interrupt index is 241, so I configure my interrupt(priority, which core to be serviced, enabled-disabled) by writing SRC[241] register of Interrupt Router(IR) also I can put my interrupt handler address to 241th index of vector table. When new byte is received by ASCLIN3, core knows ASCLIN3 RX interrupt index is 241 so it can execute 241th interrupt handler of vector table. But its different of course.  

 

1- How can I find which index of SRC of Interrupt Router for ASCLIN3 RX interrupt?

2- If there is no fixed location in vector table, and I have 2 interrupts which are ASCLIN RX and one ADC end of conversion interrupt. Both have same priority, how core knows which interrupt handle to be executed?

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cwunder
Employee
Employee
5 likes given 50 likes received 50 solutions authored

1- How can I find which index of SRC of Interrupt Router for ASCLIN3 RX interrupt?

Each SRN has one unique SRN Index Number within the Interrupt Router module. The index numbers are not required for the functionality of the interrupt router module itself. The index numbers can be used to select a Service Request Nodes for observation via the OTGM feature.

Each device has an appendix that supplies the specific implementation that supplements the family documentation. This is where you will find the specific SRC registers for the device and for the TC375 this is named “TC37x_appx_um_v2.0.pdf”. For the ASCLIN module you can go to is connectivity setting and you will find that each module has three interrupts that connect to the interrupt router.

cwunder_0-1699720993389.png

Now you look up this in these interrupt nodes to find their SRC name and address.

cwunder_1-1699720993425.png

The SRC register holds the SRPN (priority number), TOS (which CPU or DMA handles the event) and the SRE (whether or not the interrupt is enabled). The SRPN level has to match your entry in a vector table when the TOS is a CPU and its vector table.

2- If there is no fixed location in vector table, and I have 2 interrupts which are ASCLIN RX and one ADC end of conversion interrupt. Both have same priority, how core knows which interrupt handle to be executed?

Correct there is no fixed location in a vector table for the SRC this is chosen by you when writing the SCRx.SRPN and SCRx.TOS. This is one of the advantages of the TriCore where you have the freedom to choose the interrupt level priority according to your needs. You cannot have more than one priority for an interrupt in a vector table (i.e. each entry must be unique within a vector table as you can only have one entry from the linker file). If you want all interrupts, to go to one vector this can be done but then you need your own software table to redirect the response. If you need to have the different to be grouped then you can raise the interrupt level to the highest one in your group by using the BISR instruction in your ISR.

cwunder_2-1699720993448.png

With your example for example you want the interrupt priority to be 241 then your code should have something like:

 

 

 

#define SRE_ON    (1u << 10u)  /* Service Request Enable */
#define TOS_CPU0  (0u << 11u) /*TOS is for CPU0*/
#define VECTAB0 0 /*vector table for CPU 0*/
#define SRPN_INT_CPU0_ASCLIN0_TX 241 /* interrupt priority level */

void ASCLIN0_Init(void)
{
  /*your peripheral initialization code*/
  SRC_ASCLIN0TX.U  = TOS_CPU0 | SRE_ON | SRPN_INT_CPU0_ASCLIN0_TX;
}

IFX_INTERRUPT(ASCLIN0_TxISR, VECTAB0, SRPN_INT_CPU0_ASCLIN0_TX);
void ASCLIN0_TxISR(void)
{
 /*your ISR code*/
}

 

 

 

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alig
Level 1
Level 1
First reply posted First question asked Welcome!

1- I could find indexes in a document that you stated.

2- I think I understood almost everything. I will shared what I saw, it may help others.

Vector size is changing according to Vector Size Select (VSS) bit, its 32 bytes when VSS is 0, 8 bytes when VSS is 1. In my case its 32 bytes.

VecTabStartAdd.png

This vector table start address.

Prios.png

 

I set priorities like above. So indexes should be 8*32, 4*32, 24*32.

HexFile.png







You can indexes are correct but what I was expecting to see is seeing interrupt handler address in vector table.

 

HandlerAddr.png

 

 

 

This was the interrupt handler address. After searching little bit I saw there is code in vector table.

 

Disassembly.png

 

 

 

There is code in there to jump interrupt handler which saves some cycles for CPU and it reacts faster.

 

Thank you @cwunder for support.

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alig
Level 1
Level 1
First reply posted First question asked Welcome!

@cwunder  thank you for all your support.

1- I found indexes in the file you stated.

2- I was expecting to see interrupt handler address in vector table.HandlerAddr.png

 

 

 

HexFile2.png

 

But it was not in there. Then I read in architecture document there is code in there.

 

Disassembly.png

 

 

 

This code is for jumpting to interrupt handler. Also I saw vector table address offset for interrupt handlers are set like priority * 32(this changes with VSS bit), so offsets should be like 4*32, 8*32, 12*32 which are matching with hex file.

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