- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hello everyone,

In our Project we are using the EDSADC to generate the exciter signal and also read back the resolverposition.

Now to my question: our Debugger is always showing the Value 0x0F for the Filed SDCAP in the Register EDSADC_CGSYNCx. According to the manual this value should represent the phase delay between the exciter signal (after my filter stage, so it is a nice sine wave and not the pulsed signal that the EDSADC is generating) and the cosine/sine wave repsective to their channel. With an oscilloscope I measured a phase shift of about 8-9µs at a signal period of 102,4µs. In have configured 64 samples per period. So I would expect the EDSADC to show a value of about 8-9µs/102,4µs*64 = 5-6. I believe this value should give me a maximum amplitude of the Integration result, stored in IVALx.

So I did some further testing and this are the results:

So in the Graph i do not see the maximum of those integrals at 0xF which is the value of SDCAP nor on my calculated values of 5 or 6. Where is the error in my understanding?

Thanks for clarifying!

Solved! Go to Solution.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

```
In order to obtain maximum integration results (2 * Ap/pi) the AM resolver signal (Ap) has to be rectified correctly - all positive values stay positive, and all negative stay negative. As the user pointed out, the easiest way to implement rectification is to detect the zero crossing point of the AM signal.
In Aurix this is implemented in HW by the SDCOUNT counter and SDPOS capture mechanism. SDCOUNT is cleared and started upon a falling edge of the carrier’s sign signal (SGNCS), i.e. at the beginning of the positive halfwave of the carrier signal.SDCAP captures the current counter value when the first positive result is received. By reading the SDCAP value one can calculate time delay and phase shift as follows:
delay_time = SDCAP * 1M / (f_mod / CIC_FIR_decimation), in us
phase_shift = SDCAP * 360 / (NVALINT+1), in degrees
For example, if f_mod = 20MHz, CIC_FIR_decimation = 32, NVALINT = 63 and SDCAP = 0xF then
delay_time = 24us and phase_shift = 84.375 degrees.
To compensate for this delay and to synchronize the rectifier with the carrier signal, the SDPOS and SDNEG fields in the CGSYNCx registers must be set by the user application software. The user software must read the value of SDCAP for a static resolver position and set SDPOS and SDNEG as follows:
SIN signal, resolver position is between 0 degrees and 180 degrees
SDPOS = SDCAP
SDNEG = SDCAP + (NVALINT+1)/2
SIN signal, resolver position is between 180 degrees and 360 degrees
SDNEG = SDCAP
SDPOS = SDCAP + (NVALINT+1)/2
COS signal, resolver position is between 270 degrees and 90 degrees
SDPOS = SDCAP
SDNEG = SDCAP + (NVALINT+1)/2
COS signal, resolver position is between 90 degrees and 270 degrees
SDNEG = SDCAP
SDPOS = SDCAP + (NVALINT+1)/2
For every new value (any change) of the SDCAP, both the SDPOS and the SDNEG fields have to be updated.
Alternatively, one can use the SDPOS value to compute delay_time and suspend Integration for this delay. The algorithm for this sync method is given as follows:
Calculate the HW delay time: delay_time = SDCAP x 1/filterchain_frequency;
if HW delay > 0
– switch off the Integrator;
– wait for delay_time;
– enable Integrator;
It is assumed that you are not obtaining maximum amplitude after Integration due to not compensated phase_shift and not correct rectification. Please apply the above presented approaches to synchronize Rectifier with the carrier signal. Additionally, please check that the relation between f_mod and the total oversampling rate (prefilter decimation, CIC decimation, FIR0/1 decimation, number of integration cycles) fulfills the following condition OSR_tot = f_mod / f_carrier.
```

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Is there anything I can do to help clarify my question?

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hi User20530,

I will help you for consult.

dw

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Thank you, your assistance is appreciated!

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hello dw,

do I need to supply any additional data to you?

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Dear User,

I will reply you if I get info.

dw

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hi,

```
For coherent rectification, the integrator starting point must be aligned with the zero cross of the carrier to guarantee a correct calculation of the angle.
To align the integration of the AM signal with respect to the carrier, the beginning of the integration has to be delayed by a time interval equal to the roundtrip delay.
SDCAP in the CGSYNCx implements a delay measurement mechanism by counting a number of SDCOUNT cycles between the falling edge of the carrier’s sign signal (RECTCFGx.SGNCS) and the first received positive result (after negative ones).
In the ideal case with no delay between the carrier and AM signal, the SDCAP returns IWCTRx.NVALTINT+1 value, which is the number of integration cycles for one period (64 in the user's case).
In a case of delay, SDCAP returns a corresponding number of SDCOUNT counts.
Your understanding and calculations are correct.
However, it should be noted that the SDCAP value includes external HW roundtrip delay along with an internal filter chain group delay e.g. CIC3, FIR0 and FIR1.
In the user's case, the measured 8-9us time shift is an HW roundtrip delay with no internal group delay.
The SDCAP value of 0x0F presents a complete delay including filters chain group delay.
In order to align integration with the zero cross of the carrier, the SDPOS and SDNEG bitfields in the CGSYNCx should be updated for each change in the SDCAP.
Alternatively, alignment can be performed by the application as follows:
the application evaluates the SDCAP value and if it is not equal to NVALTINT+1, it stops the integrator, waits for the corresponding delay time, and restarts integration again.
```

dw

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hello dw,

sorry for the late reply, but I was on holidays.

I do not agree with the first sentence of your reply. If one already has a synchronized AM-Signal to the exciter, than it does not matter where the integration starts. It is only important to perform the integration over multiples of half a period. See my attached screenshot. I strongly believe that meassurng the zero-crossing is just the easiest way to synchronize the AM-Signal with the Exciter. But we should not argue about this.

I understand the ideal case explanation and also why the value meassuerd by the aurix controller (0xF - corresponding to a phase delay of about 24µs) is bigger than the delay that I meassured with my scope (about 8-9µs). Allthough this difference still seems a little big to me.

But even when I leave all my doubts aside I do not understand why the integration result with the ideal value of 0xF leads to a much smaller integration result than with a much smaller value for SDPOS and SDNEG respectively. Shouldn't the result be as big as possible with the ideal settings, as only then it proofs that the rectification was successfull (all positive values stayed poitive because mulitplied with +1, and all negative values got rectified because multiplied with -1)?

Thanks for claryfing!

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hi,

I will help you to consult soon.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Thank you, maybe this screenshot will help as well:

I have set up a phase delayed AM-Signal. Just from the integral values I would assume that the correct delay is one (SDPOS = 1), as this value gives the biggest integral result.

B21 holds the phase delay value that I used to create the AM-Signal from the Exciter. Also from the steps in column A you can see that I used 30° as my stepsize, so SDPOS = 1 aslo corresponds to a value of 30°.

In conclusion: I really expect the integral value to be at its maximum, when the synchronization is working correctly.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

```
In order to obtain maximum integration results (2 * Ap/pi) the AM resolver signal (Ap) has to be rectified correctly - all positive values stay positive, and all negative stay negative. As the user pointed out, the easiest way to implement rectification is to detect the zero crossing point of the AM signal.
In Aurix this is implemented in HW by the SDCOUNT counter and SDPOS capture mechanism. SDCOUNT is cleared and started upon a falling edge of the carrier’s sign signal (SGNCS), i.e. at the beginning of the positive halfwave of the carrier signal.SDCAP captures the current counter value when the first positive result is received. By reading the SDCAP value one can calculate time delay and phase shift as follows:
delay_time = SDCAP * 1M / (f_mod / CIC_FIR_decimation), in us
phase_shift = SDCAP * 360 / (NVALINT+1), in degrees
For example, if f_mod = 20MHz, CIC_FIR_decimation = 32, NVALINT = 63 and SDCAP = 0xF then
delay_time = 24us and phase_shift = 84.375 degrees.
To compensate for this delay and to synchronize the rectifier with the carrier signal, the SDPOS and SDNEG fields in the CGSYNCx registers must be set by the user application software. The user software must read the value of SDCAP for a static resolver position and set SDPOS and SDNEG as follows:
SIN signal, resolver position is between 0 degrees and 180 degrees
SDPOS = SDCAP
SDNEG = SDCAP + (NVALINT+1)/2
SIN signal, resolver position is between 180 degrees and 360 degrees
SDNEG = SDCAP
SDPOS = SDCAP + (NVALINT+1)/2
COS signal, resolver position is between 270 degrees and 90 degrees
SDPOS = SDCAP
SDNEG = SDCAP + (NVALINT+1)/2
COS signal, resolver position is between 90 degrees and 270 degrees
SDNEG = SDCAP
SDPOS = SDCAP + (NVALINT+1)/2
For every new value (any change) of the SDCAP, both the SDPOS and the SDNEG fields have to be updated.
Alternatively, one can use the SDPOS value to compute delay_time and suspend Integration for this delay. The algorithm for this sync method is given as follows:
Calculate the HW delay time: delay_time = SDCAP x 1/filterchain_frequency;
if HW delay > 0
– switch off the Integrator;
– wait for delay_time;
– enable Integrator;
It is assumed that you are not obtaining maximum amplitude after Integration due to not compensated phase_shift and not correct rectification. Please apply the above presented approaches to synchronize Rectifier with the carrier signal. Additionally, please check that the relation between f_mod and the total oversampling rate (prefilter decimation, CIC decimation, FIR0/1 decimation, number of integration cycles) fulfills the following condition OSR_tot = f_mod / f_carrier.
```

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hi User20530,

Are you still have question about this topic? As our colleague has explained, the integration has to be started at zero-crossing point to obtain maximum results. Also, carefully handle SDCAP value to use this delay for rectification shift and integration beginning point.

Thanks