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AURIX™ Forum Discussions

User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Hello everyone,

In our Project we are using the EDSADC to generate the exciter signal and also read back the resolverposition.

Now to my question: our Debugger is always showing the Value 0x0F for the Filed SDCAP in the Register EDSADC_CGSYNCx. According to the manual this value should represent the phase delay between the exciter signal (after my filter stage, so it is a nice sine wave and not the pulsed signal that the EDSADC is generating) and the cosine/sine wave repsective to their channel. With an oscilloscope I measured a phase shift of about 8-9µs at a signal period of 102,4µs. In have configured 64 samples per period. So I would expect the EDSADC to show a value of about 8-9µs/102,4µs*64 = 5-6. I believe this value should give me a maximum amplitude of the Integration result, stored in IVALx.

So I did some further testing and this are the results:

User20530_0-1656937828969.png

So in the Graph i do not see the maximum of those integrals at 0xF which is the value of SDCAP nor on my calculated values of 5 or 6. Where is the error in my understanding? 

Thanks for clarifying!

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9 Replies
User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Is there anything I can do to help clarify my question?

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dw
Moderator
Moderator 10 likes given 500 replies posted 50 likes received
Moderator

Hi User20530,

I will help you for consult.

 

dw

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User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Thank you, your assistance is appreciated!

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User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Hello dw,

do I need to supply any additional data to you?

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dw
Moderator
Moderator 10 likes given 500 replies posted 50 likes received
Moderator

Dear User,

I will reply you if I get info.

dw

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dw
Moderator
Moderator 10 likes given 500 replies posted 50 likes received
Moderator

Hi,

For coherent rectification, the integrator starting point must be aligned with the zero cross of the carrier to guarantee a correct calculation of the angle.
To align the integration of the AM signal with respect to the carrier, the beginning of the integration has to be delayed by a time interval equal to the roundtrip delay.
SDCAP in the CGSYNCx implements a delay measurement mechanism by counting a number of SDCOUNT cycles between the falling edge of the carrier’s sign signal (RECTCFGx.SGNCS) and the first received positive result (after negative ones).

In the ideal case with no delay between the carrier and AM signal, the SDCAP returns IWCTRx.NVALTINT+1 value, which is the number of integration cycles for one period (64 in the user's case).
In a case of delay, SDCAP returns a corresponding number of SDCOUNT counts.

Your understanding and calculations are correct.
However, it should be noted that the SDCAP value includes external HW roundtrip delay along with an internal filter chain group delay e.g. CIC3, FIR0 and FIR1.
In the user's case, the measured 8-9us time shift is an HW roundtrip delay with no internal group delay.
The SDCAP value of 0x0F presents a complete delay including filters chain group delay.

In order to align integration with the zero cross of the carrier, the SDPOS and SDNEG bitfields in the CGSYNCx should be updated for each change in the SDCAP.
Alternatively, alignment can be performed by the application as follows:
the application evaluates the SDCAP value and if it is not equal to NVALTINT+1, it stops the integrator, waits for the corresponding delay time, and restarts integration again.

 

dw

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User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Hello dw,

sorry for the late reply, but I was on holidays.

I do not agree with the first sentence of your reply. If one already has a synchronized AM-Signal to the exciter, than it does not matter where the integration starts. It is only important to perform the integration over multiples of half a period. See my attached screenshot. I strongly believe that meassurng the zero-crossing is just the easiest way to synchronize the AM-Signal with the Exciter. But we should not argue about this.

User20530_0-1663591629489.png

I understand the ideal case explanation and also why the value meassuerd by the aurix controller (0xF - corresponding to a phase delay of about 24µs) is bigger than the delay that I meassured with my scope (about 8-9µs). Allthough this difference still seems a little big to me.
But even when I leave all my doubts aside I do not understand why the integration result with the ideal value of 0xF leads to a much smaller integration result than with a much smaller value for SDPOS and SDNEG respectively. Shouldn't the result be as big as possible with the ideal settings, as only then it proofs that the rectification was successfull (all positive values stayed poitive because mulitplied with +1, and all negative values got rectified because multiplied with -1)?

Thanks for claryfing!

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dw
Moderator
Moderator 10 likes given 500 replies posted 50 likes received
Moderator

Hi,

I will help you to consult soon.

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User20530
Level 3
25 replies posted 10 sign-ins 5 sign-ins
Level 3

Thank you, maybe this screenshot will help as well:

User20530_0-1663595756248.png

I have set up a phase delayed AM-Signal. Just from the integral values I would assume that the correct delay is one (SDPOS = 1), as this value gives the biggest integral result.

B21 holds the phase delay value that I used to create the AM-Signal from the Exciter. Also from the steps in column A you can see that I used 30° as my stepsize, so SDPOS = 1 aslo corresponds to a value of 30°.

In conclusion: I really expect the integral value to be at its maximum, when the synchronization is working correctly.

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