I've been unable to find the exact definition of the DMEM0 and DMEM1 definitions beyond the note:
On this device, the CPU0 and CPU1 have large DSPR SRAMs. Therefore, there are two SSHs to support these
SRAMs. These are named as CPUxDMEM and CPUxDMEM1 (x=0,1).
That I've found in the TC33X/TC32X description.
Am I correct in the assumption that the smallest Aurix TC32x's with 96 kB DSPR memory have no DMEM1 instance?
TC32X and TC33X has 96 and 128kB DSPR separately. But it is not found that DMEM1 is non-existed in TC32x...