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User12907
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Hi Sir,

I am trying to offload CPU by using DMA to send out 40bytes struct on asclin1Tx with DMA. But when I set the TREL of the DMA to be 40. I will always get only 17 bytes at the receiver of the UART.
So, I guess that my DMA must over write my asclin1 TX fifo. I fixed it by breaking the DMA into 16 bytes sections and start the first transaction manually then using TX interrupt to start the next DMA
transfer as 16 bytes sections until all 40 bytes are completely sent.

Is it the correct way to do ? Are there any way for DMA to do not over write the asclin TX fifo?

Thank you very much,

Weetit
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NeMa_4793301
Level 6
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My guess is that your application is missing connecting DMA to SRC_ASCLIN1TX in the Interrupt Router. That would result in a TX overflow, because DMA needs to wait for room in the ASCLIN TX FIFO before it transfers the next byte. It makes sense that you'd only get 17 in that case: one byte in the output shift register, 16 in the TX FIFO, and the rest overflow.

Share some code and we can help straighten things out.
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User12907
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Thank you very much UC_wranler,

Here is what I do.

void initDMA(void)
{

SRC_ASCLIN1TX.B.TOS=3;
SRC_ASCLIN1TX.B.SRPN=ISR_PRIORITY_ASCLIN1_TX;
SRC_ASCLIN1TX.B.SRE=1;

/* Load default module configuration into configuration structure */
IfxDma_Dma_initModuleConfig(&g_DMA.dmaConfig, &MODULE_DMA);

/* Initialize module with configuration. */
IfxDma_Dma_initModule(&g_DMA.dmaHandle, &g_DMA.dmaConfig);

/* Get/initialize DMA channel configuration for all DMA channels otherwise use &g_Dma.dmaChannel as target */
IfxDma_Dma_initChannelConfig(&g_DMA.dmaChNCfg, &g_DMA.dmaHandle);

/* Set desired DMA channel: Channel 0 is used */
g_DMA.dmaChNCfg.channelId = DMA_CHANNEL_ID;

/* Setup the operation mode/settings for DMA channel */
g_DMA.dmaChNCfg.moveSize = IfxDma_ChannelMoveSize_8bit;
g_DMA.dmaChNCfg.blockMode = IfxDma_ChannelMove_1;
/* Set the number of DMA transfers */
g_DMA.dmaChNCfg.transferCount = (uint16)16; //<--------------------------------- Cannot make it more than 16

/* Execute the DMA transaction with only one trigger */
g_DMA.dmaChNCfg.requestMode = IfxDma_ChannelRequestMode_completeTransactionPerRequest;
g_DMA.dmaChNCfg.hardwareRequestEnabled = TRUE;
g_DMA.dmaChNCfg.requestSource=IfxDma_ChannelRequestSource_peripheral;

/* Setup the specific DMA channel configuration */
IfxDma_Dma_initChannel(&g_DMA.dmaChannel, &g_DMA.dmaChNCfg);

/* Save start address of source and destination buffers, into the Application global variable */
g_DMA.pSourceAddressForDmaTransfer = g_dataForDmaTransfer;
g_DMA.pDestinationAddressForDmaTransfer = (uint32) &ASCLIN1_TXDATA.U;
g_DMA.dmaChNCfg.sourceAddressCircularRange = IfxDma_ChannelIncrementCircular_none;
g_DMA.dmaChNCfg.sourceCircularBufferEnabled = FALSE;
g_DMA.dmaChNCfg.destinationAddressCircularRange = IfxDma_ChannelIncrementCircular_none;
g_DMA.dmaChNCfg.destinationCircularBufferEnabled = TRUE;

g_DMA.dmaChNCfg.operationMode = IfxDma_ChannelOperationMode_continuous;

}

/* Trigger a DMA transaction via SW request */
static void triggerDMATransfer(void)
{
/* Set destination and source address data to DMA channel */
g_DMA.dmaChNCfg.sourceAddress = (uint32) g_DMA.pSourceAddressForDmaTransfer;
g_DMA.dmaChNCfg.destinationAddress = (uint32) g_DMA.pDestinationAddressForDmaTransfer;
IfxDma_Dma_initChannel(&g_DMA.dmaChannel, &g_DMA.dmaChNCfg);

/* Request start of DMA Transaction channel 0 */
IfxDma_Dma_startChannelTransaction(&g_DMA.dmaChannel);
}
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NeMa_4793301
Level 6
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I don't see anything about ASCLIN initialization.
Is ASCLIN1_FLAGSENABLE.TFLE set?
What's in ASCLIN1_TXFIFOCON.INTLEVEL?

Is ISR_PRIORITY_ASCLIN1_TX equal to DMA_CHANNEL_ID?

This looks a little fishy, because it will try to do all the bytes in one go:

/* Execute the DMA transaction with only one trigger */
g_DMA.dmaChNCfg.requestMode = IfxDma_ChannelRequestMode_completeTransactionPerRequest;

I would try this instead, so that each TXFIFO empty causes one DMA byte transfer:

/* Execute one DMA transfer per trigger */
g_DMA.dmaChNCfg.requestMode = IfxDma_ChannelRequestMode_oneTransferPerRequest;
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User12907
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Hi UC_wranger,

I think I set ASCLIN1_TXFIFOCON.INTLEVEL to 0.
I have try set g_DMA.dmaChNCfg.requestMode = IfxDma_ChannelRequestMode_oneTransferPerRequest; but still no luck.

Here is the init for uart

void init_asc_uart()
{
IfxAsclin_Asc_Config ascConfig;
IfxAsclin_Asc_initModuleConfig(&ascConfig, &MODULE_ASCLIN1);

ascConfig.baudrate.baudrate = 921600;

ascConfig.interrupt.txPriority = INTPRIO_ASCLIN1_TX;
ascConfig.interrupt.rxPriority = INTPRIO_ASCLIN1_RX;
ascConfig.interrupt.typeOfService = IfxSrc_Tos_dma;

const IfxAsclin_Asc_Pins pins =
{
NULL_PTR, IfxPort_InputMode_pullUp, /* CTS pin not used */
&IfxAsclin1_RXA_P15_1_IN, IfxPort_InputMode_pullUp, /* RX pin */
NULL_PTR, IfxPort_OutputMode_pushPull, /* RTS pin not used */
&IfxAsclin1_TX_P15_0_OUT, IfxPort_OutputMode_pushPull, /* TX pin */
IfxPort_PadDriver_cmosAutomotiveSpeed1
};
ascConfig.pins = &pins;

ascConfig.txBuffer = &g_ascTxBuffer;
ascConfig.txBufferSize = UART_TX_BUFFER_SIZE;
ascConfig.rxBuffer = &g_ascRxBuffer;
ascConfig.rxBufferSize = UART_RX_BUFFER_SIZE;

ascConfig.fifo.txFifoInterruptLevel=IfxAsclin_TxFifoInterruptLevel_0;

IfxAsclin_Asc_initModule(&g_ascHandle, &ascConfig); /* Initialize module with above parameters */
}
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teoBits
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Hello,

did you take a look at the UART_DMA_Transfer_1_KIT_TC297_TFT training and its tutorial?

The training is written for AURIX TC297 but it can be easily ported for your device also.

hope it helps,
teoBits
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User12907
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Hi Teo,

Yes that one is Uart RX to DMA, in this case RX fifo will not be overflowed with the DMA. For my case, DMA to Uart TX. I cannot make DMA wait for the TX fifo, the DMA keep pump the data until UART TX fifo over flow.
The current solution now, it sets DMA move to be 16 as the fifo size and use TX interrupt (set to filo level=0) to start next DMA transfer 16 bytes a time, until all the data is transferred. This works but it is not 100% DMA.
So, I would like to know if it is possible to offload CPU 100% making DMA and UART TX fifo works together.


Best Regards,
Weetit
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cwunder
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Perhaps this helps, this example is for the TC297 but should be basically the same for the TC265. It uses ASCLIN0 and two DMA channels one for Tx and Rx.

I didn't use the iLLD's. To trigger a transmit you can do the following assuming you have the DMA ready:
/* Initiate the transmit transfer using the transmit FIFO level flag */
ASCLIN0_FLAGSSET.B.TFLS = 1;

Here is the ASCLIN file

/****** ASCLIN0 PORT Selection ******************************/
/* [0] ATX0:P14.00 ARX0A:P14.01 */
/* [1] ATX0:P15.02 ARX0B:P15.03 */
/* [2] ATX0:P01.13 ARX0C:P01.08 */
/* [3] ATX0:P34.01 ARX0D:P34.02 */
/* [4] ATX0:P13.10 ARX0E:P13.11 */
#define ASCLIN0_PORT 1

#if (ASCLIN0_PORT == 0)
#define IOCR_ALTI asclin_iocr_RxInputSelect_ARXnA
#define ASCLIN0_PD_PIN P14_PDR0.B.PD0 = 0
#define ASCLIN0_TX_PIN P14_IOCR0.B.PC0 = PCx_Output_PushPull_Alt_2
#define ASCLIN0_RX_PIN P14_IOCR0.B.PC1 = PCx_Input_PullUp
#elif (ASCLIN0_PORT == 1)
#define IOCR_ALTI asclin_iocr_RxInputSelect_ARXnB
#define ASCLIN0_PD_PIN P15_PDR0.B.PD2 = 0
#define ASCLIN0_TX_PIN P15_IOCR0.B.PC2 = PCx_Output_PushPull_Alt_2
#define ASCLIN0_RX_PIN P15_IOCR0.B.PC3 = PCx_Input_PullUp
#elif (ASCLIN0_PORT == 2)
#define IOCR_ALTI asclin_iocr_RxInputSelect_ARXnC
#define ASCLIN0_PD_PIN P01_PDR1.B.PD13 = 0
#define ASCLIN0_TX_PIN P01_IOCR12.B.PC13 = PCx_Output_PushPull_Alt_2
#define ASCLIN0_RX_PIN P01_IOCR8.B.PC8 = PCx_Input_PullUp
#elif (ASCLIN0_PORT == 3)
#define IOCR_ALTI asclin_iocr_RxInputSelect_ARXnD
#define ASCLIN0_PD_PIN P34_PDR0.B.PD1 = 0
#define ASCLIN0_TX_PIN P34_IOCR0.B.PC1 = PCx_Output_PushPull_Alt_2
#define ASCLIN0_RX_PIN P34_IOCR0.B.PC2 = PCx_Input_PullUp
#elif (ASCLIN0_PORT == 4)
#define IOCR_ALTI asclin_iocr_RxInputSelect_ARXnE
#define ASCLIN0_PD_PIN P13_PDR1.B.PD10 = 0
#define ASCLIN0_TX_PIN P13_IOCR8.B.PC10 = PCx_Output_PushPull_Alt_2
#define ASCLIN0_RX_PIN P13_IOCR8.B.PC11 = PCx_Input_PullUp
#else
#error "No ASCLIN0 pins defined"
#endif

/* private data */
static volatile uint16 ASCLIN0_errorCount;
static volatile uint16 ASCLIN0_txDmaCnt;
static volatile uint16 ASCLIN0_rxDmaCnt;

void ASCLIN0_Init (void)
{
uint16 cpuPassword = IfxScuWdt_getCpuWatchdogPassword();
IfxScuWdt_clearCpuEndinit(cpuPassword);
ASCLIN0_CLC.U = 0; /* enable peripheral and allow sleep mode */
(void) ASCLIN0_CLC.U;
/* change the driver strength on the port transmit pin */
ASCLIN0_PD_PIN;

/* Kernel reset */
ASCLIN0_KRST0.U = 0x01;
ASCLIN0_KRST1.U = 0x01;
IfxScuWdt_setCpuEndinit(cpuPassword);

while ((ASCLIN0_KRST0.U & 0x02) != 0x02)
;
IfxScuWdt_clearCpuEndinit(cpuPassword);
ASCLIN0_KRSTCLR.U = 0x01; /* Clear Reset done flag */
IfxScuWdt_setCpuEndinit(cpuPassword);

/* ASCLIN0_ATX transmit output */
ASCLIN0_TX_PIN;
/* ASCLIN0 ARX0n receive pin*/
ASCLIN0_RX_PIN;

Ifx_ASCLIN_IOCR iocr = {
.B.ALTI = IOCR_ALTI,
.B.DEPTH = 0, /*0=off, 1 to 63 */
.B.CTS = asclin_iocr_CtsInputSelect_0,
.B.RCPOL = asclin_iocr_RtsCtsPolarity_activeHigh,
.B.CPOL = asclin_iocr_ClockPolaritySyncMode_idleLow,
.B.SPOL = asclin_SlavePolaritySyncModeSlsoIdleLow,
.B.LB = asclin_iocr_LoopBackModeDisabled,
.B.CTSEN = asclin_iocr_CTS_disabled,
};
ASCLIN0_IOCR.U = iocr.U;

Ifx_ASCLIN_TXFIFOCON txfifocon = {
.B.FLUSH = asclin_txfifocon_Flushed,
.B.ENO = asclin_txfifocon_OutletEnabled,
.B.INW = asclin_txfifocon_InletWidth_1,
.B.INTLEVEL = asclin_txfifocon_InterruptLevel_15,
};
ASCLIN0_TXFIFOCON.U = txfifocon.U;

Ifx_ASCLIN_RXFIFOCON rxfifocon = {
.B.FLUSH = asclin_rxfifocon_Flushed,
.B.ENI = asclin_rxfifocon_InletEnabled,
.B.OUTW = asclin_rxfifocon_OutletWidth_1,
.B.INTLEVEL = asclin_rxfifocon_InterruptLevel_1,
.B.BUF = asclin_rxfifocon_ReceiveBufferMode_rxFifo,
};
ASCLIN0_RXFIFOCON.U = rxfifocon.U;

Ifx_ASCLIN_FRAMECON framecon = {
.B.ODD = asclin_ParityType_even,
.B.PEN = asclin_ParityEnable_Disabled,
.B.CEN = asclin_CollisionDetection_Disabled,
.B.MSB = asclin_ShiftDirection_lsbFirst,
.B.MODE = asclin_frameMode_initialise,
.B.LEAD = asclin_LeadDelay_0,
.B.STOP = asclin_StopBit_1,
.B.IDLE = asclin_IdleDelay_0,
};
ASCLIN0_FRAMECON.U = framecon.U;

Ifx_ASCLIN_DATCON datcon = {
.B.RESPONSE = 0,
.B.CSM = asclin_Checksum_classic,
.B.RM = asclin_LinResponseTimeoutMode_frameTimeout,
.B.HO = asclin_HeaderResponseSelect_headerAndResponse,
.B.DATLEN = asclin_DataLength_8,
};
ASCLIN0_DATCON.U = datcon.U;

Ifx_ASCLIN_BITCON bitcon = {
.B.SM = asclin_SamplesPerBit_three,
.B.SAMPLEPOINT = asclin_SamplePointPosition_9,
.B.OVERSAMPLING = asclin_OversamplingFactor_16,
.B.PRESCALER = 0,
};
ASCLIN0_BITCON.U = bitcon.U;

/*this will configure the baud rate to 115200*/
Ifx_ASCLIN_BRG brg = {
.B.NUMERATOR = 71,
.B.DENOMINATOR = 3852,
};
ASCLIN0_BRG.U = brg.U;

/* Clear all Flags */
ASCLIN0_FLAGSCLEAR.U = 0xFFFFFFFF;

Ifx_ASCLIN_FLAGSENABLE flagenable = {
.B.TFLE = TRUE, /* Transmit FIFO Level */
.B.TFOE = TRUE, /* Transmit FIFO Overflow */
.B.RFLE = TRUE, /* Receive FIFO Level */
.B.RFUE = TRUE, /* Receive FIFO Underflow */
.B.RFOE = TRUE, /* Receive FIFO Overflow */
.B.FEE = TRUE, /* Framing Error */
};
ASCLIN0_FLAGSENABLE.U = flagenable.U;

/*set up the interrupts that are used */
SRC_ASCLIN0TX.U = TOS_DMA | SRE_ON | SRPN_DMA_CH_ASCLIN0_TX;
SRC_ASCLIN0RX.U = TOS_DMA | SRE_ON | SRPN_DMA_CH_ASCLIN0_RX;
SRC_ASCLIN0ERR.U = TOS_CPU0 | SRE_ON | SRPN_CPU0_ASCLIN0_ER;

/*set the mode of the ASCLIN to operate in*/
ASCLIN0_FRAMECON.B.MODE = asclin_frameMode_asc;

Ifx_ASCLIN_CSR csr = {
.B.CLKSEL = asclin_csr_ClockSource_fASCLINS,
.B.CON = asclin_csr_ClockIsOn,
};
ASCLIN0_CSR.U = csr.U;
}

void ASCLIN0_DMA_Init (uint32 *src, uint32 *dst, uint16 trel)
{
/* DMA Channel 007 used for Transmit */
DMA_SADR007.U = (uint32) src;
DMA_DADR007.U = (uint32) &ASCLIN0_TXDATA.U;


Ifx_DMA_CH_CHCFGR chcfgr_7 = {
.B.TREL = trel, /*Transfer Reload Value */
.B.BLKM = dma_chcfgrxxx_blkm_OneTransferHasOneMove,
.B.RROAT = dma_chcfgrxxx_rroat_ResetAfterEachTransfer,
.B.CHMODE = dma_chcfgrxxx_chmode_SingleMode,
.B.CHDW = dma_chcfgrxxx_chdw_DataBitWidth_8,
.B.PATSEL = dma_chcfgrxxx_patsel_NoPatternCompareOperation,
.B.PRSEL = dma_chcfgrxxx_prsel_HardwareRequestSelected,
.B.DMAPRIO = dma_chcfgrxxx_dmaprio_LowPrioritySelected,
};
DMA_CHCFGR007.U = chcfgr_7.U;

Ifx_DMA_CH_ADICR adicr_7 = {
.B.SMF = dma_adicrxxx_smf_AddressOffsetIsCHDWx1,
.B.INCS = dma_adicrxxx_incs_AddressOffsetIsAdded,
.B.DMF = dma_adicrxxx_dmf_AddressOffsetIsCHDWx1,
.B.INCD = dma_adicrxxx_incd_AddressOffsetIsSubtracted,
.B.CBLS = dma_adicrxxx_cbls_SourceAddress31to0,
.B.CBLD = dma_adicrxxx_cbld_DestinationAddress31to0,
.B.SHCT = dma_adicrxxx_shct_MoveOperation,
.B.SCBE = dma_adicrxxx_scbe_SourceCircularBufferDisabled,
.B.DCBE = dma_adicrxxx_dcbe_DestinationCircularBufferEnabled,
.B.STAMP = dma_adicrxxx_stamp_NoAction,
.B.ETRL = dma_adicrxxx_etrl_NoInterruptOnLostEvent,
.B.WRPSE = dma_adicrxxx_wrpse_WrapSourceBufferInterruptTriggerDiabled,
.B.WRPDE = dma_adicrxxx_wrpde_WrapDestinationBufferInterruptTriggerDiabled,
.B.INTCT = dma_adicrxxx_intct_InterruptChangingTCOUNTandEqualsIRDV,
.B.IRDV = 0, /*Interrupt Raise Detect Value*/
};
DMA_ADICR007.U = adicr_7.U;
DMA_TSR007.B.ECH = 1;

/* DMA Channel 008: used for Receive */
DMA_SADR008.U = (uint32) &ASCLIN0_RXDATA.U;
DMA_DADR008.U = (uint32) dst;

Ifx_DMA_CH_CHCFGR chcfgr_8 = {
.B.TREL = trel, /*Transfer Reload Value */
.B.BLKM = dma_chcfgrxxx_blkm_OneTransferHasOneMove,
.B.RROAT = dma_chcfgrxxx_rroat_ResetAfterEachTransfer,
.B.CHMODE = dma_chcfgrxxx_chmode_SingleMode,
.B.CHDW = dma_chcfgrxxx_chdw_DataBitWidth_8,
.B.PATSEL = dma_chcfgrxxx_patsel_NoPatternCompareOperation,
.B.PRSEL = dma_chcfgrxxx_prsel_HardwareRequestSelected,
.B.DMAPRIO = dma_chcfgrxxx_dmaprio_LowPrioritySelected,
};
DMA_CHCFGR008.U = chcfgr_8.U;

Ifx_DMA_CH_ADICR adicr_8 = {
.B.SMF = dma_adicrxxx_smf_AddressOffsetIsCHDWx1,
.B.INCS = dma_adicrxxx_incs_AddressOffsetIsSubtracted,
.B.DMF = dma_adicrxxx_dmf_AddressOffsetIsCHDWx1,
.B.INCD = dma_adicrxxx_incd_AddressOffsetIsAdded,
.B.CBLS = dma_adicrxxx_cbls_SourceAddress31to0,
.B.CBLD = dma_adicrxxx_cbld_DestinationAddress31to0,
.B.SHCT = dma_adicrxxx_shct_MoveOperation,
.B.SCBE = dma_adicrxxx_scbe_SourceCircularBufferEnabled,
.B.DCBE = dma_adicrxxx_dcbe_DestinationCircularBufferDisabled,
.B.STAMP = dma_adicrxxx_stamp_NoAction,
.B.ETRL = dma_adicrxxx_etrl_NoInterruptOnLostEvent,
.B.WRPSE = dma_adicrxxx_wrpse_WrapSourceBufferInterruptTriggerDiabled,
.B.WRPDE = dma_adicrxxx_wrpde_WrapDestinationBufferInterruptTriggerDiabled,
.B.INTCT = dma_adicrxxx_intct_InterruptChangingTCOUNTandEqualsIRDV,
.B.IRDV = 0, /*Interrupt Raise Detect Value*/
};
DMA_ADICR008.U = adicr_8.U;
DMA_TSR008.B.ECH = 1;

/* Setup interrupt from DMA Channel 7 and 8 when the Move Transaction has finished */
SRC_DMACH7.U = TOS_CPU0 | SRE_ON | SRPN_CPU0_DMA_CH7;
SRC_DMACH8.U = TOS_CPU0 | SRE_ON | SRPN_CPU0_DMA_CH8;
}


Scope plot of the output for the first 20 bytes (i have P15.2 connected to P15.3 with an external jumper)
5160.attach
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User12907
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cwunder wrote:
Perhaps this helps, this example is for the TC297 but should be basically the same for the TC265. It uses ASCLIN0 and two DMA channels one for Tx and Rx.


Hi cwunder,

I will try this Thank you very much.

Best Regards,

Weetit
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User21192
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Can someone explain to me, in words maybe, how the FIFO and the DMA communicate? I see the FIFO overflowing so I get the 17 bytes too, but I just don't see the mechanism that allows the handshaking.
thanks in advance,
Charlie
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NeMa_4793301
Level 6
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In general: DMA gets fed by the Interrupt Router. So it's a matter of configuring a peripheral to assert an interrupt (aka service request).

In the example cwunder posted, the TX/RX interrupts from the FIFO are enabled setting ASCLIN0_FLAGSENABLE, and then the interrupt feeds DMA by configuring the Interrupt Router via SRC_ASCLIN0TX and SRC_ASCLIN0RX.
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User21192
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SRC_ASCLIN0TX.U = TOS_DMA | SRE_ON | SRPN_DMA_CH_ASCLIN0_TX;
in this line,
TOS_DMA = (1 << 11)
SRE_ON = (1<<10)
but what does SRPN_DMA_CH_ASCLIN0_TX equal? would it be 7, the DMA channel number?

thanks again, Charlie
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cwunder
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CharlieK wrote:
but what does SRPN_DMA_CH_ASCLIN0_TX equal? would it be 7, the DMA channel number?

Correct, the DMA channel for TX is 7 and for RX is 8 for that example.
5223.attach
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User21192
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I finally got it. Thank you all for the help.

I was trying to start the process of sending by doing this:
DMA_CHCSR047.B.SCH = 1; // start transfers to complete a transaction
which was wrong. It didn't start the FIFO going with the help of the interrupt router.

/* Initiate the transmit transfer using the transmit FIFO level flag */
ASCLIN8_FLAGSSET.B.TFLS = 1;
is what I needed to do.
It was clearly stated in the sample provided. I just didn't comprehend it.
Charlie
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User22621
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hi weetit,
Does your problem has been resolved? I met the same problem, I want to send 32 bytes, but the receiver only got 17 bytes.
If your problem has been resolved, would you share me your solution?
Thank you~
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