Mar 16, 2020
10:44 AM
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Mar 16, 2020
10:44 AM
Hello,
I need to put the TC212 on sleep mode, and I have 4 external condition for exit and come back in normal mode.
What are the pins that can be set for these external interrupts? Is it possible to use the pins with SCU_REQx function?
Thank you in advance.
I need to put the TC212 on sleep mode, and I have 4 external condition for exit and come back in normal mode.
What are the pins that can be set for these external interrupts? Is it possible to use the pins with SCU_REQx function?
Thank you in advance.
- Tags:
- aurix tc212
- IFX
3 Replies
Mar 16, 2020
06:29 PM
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Mar 16, 2020
06:29 PM
Have you reviewed Figure 8-35 External Request Unit Input Connections for TC22x/TC23x in the user's manual?
Mar 17, 2020
01:49 AM
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Mar 17, 2020
01:49 AM
Thank you sir,
I was not sure that ERSx can wake-up the uC from sleep mode, as I can't find ERSx fields into the "Standby and Wake-up Control Registers 0-3".
So, once configured the several ERSi to have the connections with REQx which fields and which registers should be set to have the wake-up from them?
THank you.
I was not sure that ERSx can wake-up the uC from sleep mode, as I can't find ERSx fields into the "Standby and Wake-up Control Registers 0-3".
So, once configured the several ERSi to have the connections with REQx which fields and which registers should be set to have the wake-up from them?
THank you.
Mar 17, 2020
04:49 AM
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Mar 17, 2020
04:49 AM
You stated that you wanted "Sleep Mode"...
From the manual:
System may enter Sleep Mode on following events:
• On a SW Sleep request issued by setting PMCSR0.REQSLP = 10B by the CPU.
CPU code execution is halted and CPU Idle state is entered. Peripherals are set into sleep state if so configured in the respective CLCx.EDIS bit. Ports retain their earlier programmed state.
System may exit Sleep mode on following events:
• When an interrupt or trap is issued to a CPU.
• When an NMI trap event takes place.
• When the CPU watchdog or Safety watchdog timer overflow events trigger an SMU alarm leading in turn to a CPU interrupt.
• When a MSB bit wrap of CPU Watchdog counter takes place.
• When an Application reset, System reset or any higher reset occurs
From the manual:
System may enter Sleep Mode on following events:
• On a SW Sleep request issued by setting PMCSR0.REQSLP = 10B by the CPU.
CPU code execution is halted and CPU Idle state is entered. Peripherals are set into sleep state if so configured in the respective CLCx.EDIS bit. Ports retain their earlier programmed state.
System may exit Sleep mode on following events:
• When an interrupt or trap is issued to a CPU.
• When an NMI trap event takes place.
• When the CPU watchdog or Safety watchdog timer overflow events trigger an SMU alarm leading in turn to a CPU interrupt.
• When a MSB bit wrap of CPU Watchdog counter takes place.
• When an Application reset, System reset or any higher reset occurs