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FD_aurix
Level 5
Level 5
100 sign-ins 100 replies posted 5 solutions authored

Hi all

I'm trying to relocate some variable from one core to the other using 

#pragma data_core_association private0/1/2

I notice that the variable is moved from dsram  to psram  there is a way to decide where to relocate the variable?

e.g.

static uint32_t bar;   -> bar  located into dsram0

 

#pragma data_core_association private0

static uint32_t bar;  -> bar  located into psram0

#pragma data_core_association restore

Thanks

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1 Solution
Di_W
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 100 likes received

Hi FD,

I have asked for internal team and perhaps this is needed to ask compiler tech support, please notice that the Tasking free toolchain's support is limited. However you could use the workaround first.

Besides, there is a PSPR code sample for your reference:

 

//_____________________________Locate test for CPU0 related pspr code_________________________________

#if defined(__TASKING__)
#pragma section code "psram_text_cpu0"
#elif defined(__GNUC__)
#pragma section ".psram_text_cpu0" axw
#elif defined(__DCC__)
#pragma section CODE ".psram_text_cpu0" standard RXW
#elif defined(__ghs__)
#pragma ghs section text=".psram_text_cpu0"
#endif

uint32 Locate_PsprCode_fc0(void)
{
	return retData0;
}

#if defined(__GNUC__)
#pragma section
#endif

 

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8 Replies
Di_W
Moderator
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Moderator
1000 replies posted 250 solutions authored 100 likes received

Hi FD_aurix,

I have found an example from https://github.com/Infineon/AURIX_code_examples/blob/288e353e583148009bd03c16d65db76370cba1af/code_e...

You could check if .lsl file has some section names you could use.

 Above is for your reference.

Or you can check the compiler's user manual for details. i.e.https://www.tasking.com/support/tricore/ctc_user_guide_v6.3r1.pdf

 

 

dw

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FD_aurix
Level 5
Level 5
100 sign-ins 100 replies posted 5 solutions authored

Hi dw

Thanks for the reply. 

I've checked the manual and the private memory qualifier should "Preferably in core n local RAM. If the memory is full, other memory is used."  But it is not specified what is the "local RAM" and for sure the DSRAM of this core is not full 😄

in the example it is used the #pragma section that seems only a renaming  features

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Di_W
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 100 likes received

Dear Users,

Please refer to below link, I have tried DLMU0-5/ DSPR0-5/ and LMU.

Note that edmem and psram I have not tried.

You can use the same way to your application. The .lsl file is attached.

https://community.infineon.com/t5/AURIX/Unable-to-read-write-to-DLMU/m-p/346011/highlight/true#M7253

dw

FD_aurix
Level 5
Level 5
100 sign-ins 100 replies posted 5 solutions authored

Hi dw

yes, this will works and it is a possible solution but it will be necessary to specify for each type of variable (neardata, fardata,nearbss etc) the ram location. There should be a method using "pragma data_core_association " and it works but it also change the location from dsram to psram (at least using the ADS linker file)

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Di_W
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1000 replies posted 250 solutions authored 100 likes received

 

#pragma data_core_association private0

 uint32 bar0; // -> bar  located into psram0

#pragma data_core_association restore
#pragma data_core_association private1

 uint32 bar1; // -> bar  located into psram1

#pragma data_core_association restore
#pragma data_core_association private2

 uint32 bar2; // -> bar  located into psram2

#pragma data_core_association restore
__private0 uint32 bar0;
__private1 uint32 bar1;
__private2 uint32 bar2;

 

dw_0-1651059926915.png

Hi FD,

I have used pragma data_core_association as above code showed, and found PSRAM0/1/2 is allocated from local PSPR memory (start address 0xc0000000). I will report to internal team for investigate.

Thanks!

dw

 

FD_aurix
Level 5
Level 5
100 sign-ins 100 replies posted 5 solutions authored

yes, I expect it will be mapped on DSram

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FD_aurix
Level 5
Level 5
100 sign-ins 100 replies posted 5 solutions authored

Did you get some feedback?

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Di_W
Moderator
Moderator
Moderator
1000 replies posted 250 solutions authored 100 likes received

Hi FD,

I have asked for internal team and perhaps this is needed to ask compiler tech support, please notice that the Tasking free toolchain's support is limited. However you could use the workaround first.

Besides, there is a PSPR code sample for your reference:

 

//_____________________________Locate test for CPU0 related pspr code_________________________________

#if defined(__TASKING__)
#pragma section code "psram_text_cpu0"
#elif defined(__GNUC__)
#pragma section ".psram_text_cpu0" axw
#elif defined(__DCC__)
#pragma section CODE ".psram_text_cpu0" standard RXW
#elif defined(__ghs__)
#pragma ghs section text=".psram_text_cpu0"
#endif

uint32 Locate_PsprCode_fc0(void)
{
	return retData0;
}

#if defined(__GNUC__)
#pragma section
#endif

 

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