Aurix Dev kit HWCFG

[rauhkvi]

We are using a Aurix development kit for a kick off of a project. Upon reset of the board, during flashing, some of the GPIO pins go high and cause other devices to trigger causing a non-resettable failure on an auxiliary device. So GPIO needs to be set to high impedance on reset which I found can be done with the HWCFG6 pin. On the dev board P14.4 (HWCGF[6]) is left floating, pulling this down using the provided resistor pad, per the documentation should fix this. But when I do that the board is in a constant reset state ESR0 LED is constant on.  Is there a different way of changing this in SW or HW so GPIO is in high impedance state but without triggering a constant reset?

[Di_W · Accepted solution]

Hi rauhkvi,

In AURIXTC3XX_um_part1_v2.0.pdf, page 127, Figure 21, ESR0 handling is followed by Jump to User Code.

So, have you checked ESR0 pin status at start of your application code?

Gernerally, ESR0 will be High after Firmware END and ESR0 LED will be dimmed.

Otherwise, PMSWCR5.TRISTREQ is set to override initial latched status from HWCFG[6].

BPTRISTREQ is Bit protection for Tristate request bit (TRISTREQ) Setting this bit enables that bit TRISTREQ can be changed by a write operation.

dw