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Sven
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What are the preconditions for EVFLAG register to display new results (channel flags set to 1 at new inputs)?

currently it displays 0 permanently.

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Di_W
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Hi Sven,

26.8 Result events: indicate the availability of new valid results. Usually, this triggers a read action by CPU or DMA. Result events are generated at the output rate of the configured filter chain (indicated by bits RESEVx in register EVFLAG). The output rate of result service requests depends on the selected FIFO fill level (see bitfield SRLVL in register RFCx (x=0-{13})). Can be issued via SRxM.

AURIXTC3XX_TS_V1.3.0.PDF 

dw

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Sven
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thanks, a routine to observe RESEVx in EVFLAG register is deployed; but it gets 0 values only.
It seems, some preconditions to run EVFLAG on Infineon Eval Board are not fulfilled.

So you suggest to check the output rate configuration - FIFO fill level (SRLVL in RFCx register) - as precondition part.
I started using Aurix products, currently EDsadc initialization.

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Di_W
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500 solutions authored 1000 replies posted 250 solutions authored

Please refer to AP32561-Tutorial_TC3xx_SiMIc_with_EDSADC_v1.0.2 You can download from myICP.

dw_0-1646986633833.png

dw

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Sven
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where do i need to navigate for the AP32561-Tutorial_TC3xx_SiMIc_with_EDSADC_v1.0.2 docu?

I am registered on MyICP; putting the name in search field provided no results.

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Di_W
Moderator
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500 solutions authored 1000 replies posted 250 solutions authored
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Sven
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thanks, seems a NDA here additionally required, i organize

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