Aurix 2G User Manual containing Memory Order related sections missing

[User9635]

Hello Support,
Shown below snippets from XMC4500 User Manual of Infineon
Infineon-xmc4500_rm_v1.6_2016-UM-v01_06-EN-598157.pdf
which describes Memory Order related stuff within XMC4500 Family of MCU.
I am looking for similar Memory Order related stuff for Aurix 2G User Manual.
Can you please provide me reference to section from Aurix 2G User Manual which describes Memory Order related stuff similar to snippets shown below?



Best Regards

[Darren_Galpin]

Having just gone through the manual, there isn't an equivalent section, but equally the XMC is not an equivalent to the Aurix architecture either, and they have different processor cores. The information required is spread through chapter 5, the CPU subsystem - maybe look at 5.6.9 Atomicity of data accesses, 5.7 Memory Addressing, 5.9 CPU Instruction Timing, and look at the DSYNC command in the instruction set manual.

[User9635]

Hello Support,
Does Store Buffers also remain in the Write Signal Path when CPU Core Writes to Any Peripheral Register Address ranges?
Best Regards

[NeMa_4793301]

I'm not sure what you mean with Write Signal Path - but all writes outside of DSPR use Store Buffers.

[User9635]

Hello Support,
That means if CPU writes to Peripheral Register Address and then Read back from the same Peripheral Register Address as the next instruction, all further CPU Peripheral Memory Access Cycle will be stalled till Peripheral Store action completes because Store Buffer will not alter the Store/Load sequence for Peripheral Access.
Correct?
Best Regards

[cwunder]

There is a chapter in the user's manual talking about the store buffers. This is chapter 5.3.4.3 Store Buffers:

In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless:
• The store buffer is full.
• The load is to peripheral space and a store to peripheral space exists in the store buffer. (In order peripheral space access).
• The load or store is part of a read-modify-write operation.

You case is covered by bullet number 2