AURIX™ Forum Discussions

[User9635]

Hello Support,

According to Aurix 2G User Manual, RSTCON2.USRINFO contents shall survive all Warm Reset.
But in my code I find that after LBIST Execution when Warm Reset occurs, then RSTCON2.USRINFO contents are cleared to zero,
Is it an Errata?
Please help.
Best Regards

[cwunder]

This not an errata. In section 9.3.3.1.1 Functional Description: All the digital logic of the device with two exceptions is covered by LBIST. I would not think the RSTCON2.USRINFO information would be maintained as this would be tested.

Added link to your other post where the user's manual states the SSW considers this a "cold" reset from UC_wrangler.
https://www.infineonforums.com/threads/11131-LBIST-Run-Completion-Reset-and-RAMIN-field-of-HF_PROCON...

[User9635]

Hello Support,

Is there any register within Aurix 2G whose values are maintained same across LBIST Reset occurrence?

Best Regards

[NeMa_4793301]

The Standby Controller XRAM (0xF0240000-0xF0241FFF) is not affected by LBIST.

[User9635]

Hello Support,

I wrote some magic number to one unisigned in within XRAM ((0xF0240000-0xF0241FFF).
After LBIST reset, I see that memory is zero,
Can you please check on your side on Triboard and let me know, if indeed XRAM should maintain its contents on LBIST Reset?
HF_PROCONRAM = 0x02.

Best Regards

[cwunder]

Can you please check on your side on Triboard and let me know, if indeed XRAM should maintain its contents on LBIST Reset?

FWIW I ran the LBIST (successfully) on a TC389 TriBoard with HF_PROCONRAM=0 (clear Init_All, RAM initialization is performed after cold power-on- reset and warm power-on-reset)
The contents are maintained at address 0xF02400000 and for another alternative in the MCMCAN @ 0xF0200000 (albeit you need to enable the MCMCAN CLC register)

[User9635]

Hello Support,
Thank you for trying it out.
"The Standby Controller XRAM (0xF0240000-0xF0241FFF) is not affected by LBIST. "
Is this XRAM available for CPU when the PMSWCR4.SCREN=0 -- Bit 25 of PMSWCR4 Register is zero.
Please confirm.
Best Regards

[User9635]

Hello Support,
Can you please answer to the last question?
Best regards

[cwunder]

baexps_pr1 wrote:

Is this XRAM available for CPU when the PMSWCR4.SCREN=0 -- Bit 25 of PMSWCR4 Register is zero.

Yes it is available for everyone except the SCR as you have disabled it.

[User9635]

Hello Support,
According to User Manual, SCU_PMSWCR1 will be reset of Cold Power On Reset.
Does it mean, it will also reset on LBIST Reset?

Best Regards

[NeMa_4793301]

Yes it will also reset.

[User9635]

Hello Support,
On March 11, you wrote the following in this mail trail :

"FWIW I ran the LBIST (successfully) on a TC389 TriBoard with HF_PROCONRAM=0 (clear Init_All, RAM initialization is performed after cold power-on- reset and warm power-on-reset)
The contents are maintained at address 0xF02400000 and for another alternative in the MCMCAN @ 0xF0200000 (albeit you need to enable the MCMCAN CLC register)
"
For the XRAM contents, before running LBIST, did you clear the existing RSTSTAT bits by using RSTCON2.CLRC?
Or, RSTSTAT bits were same as Cold Power On -- that means PORST=1 and STBYR=1 when you ran the LBIST?
What I am finding is that if I don't clear the RSTSTAT.PORST and RSTSTAT.STBYR before running LBIST by using RSTCON2.CLRC=1, then XRAM is also being initialized by LBIST Reset.
Can you please confirm under what condition does XRAM initialize while running LBIST?
That will help me better understand the control flow of the code I am running for debugging.
I am somewhat confused now. Your help is much appreciated.
May be you can provide me the snippets of user manual for the exact behavior of XRAM initialization under various conditions.
Best Regards

[User9635]

Hello Support,

Can you please confirm the last question I asked above about XRAM initialization when RSTCON2.CLRC=1 before LBIST execution?
Best Regards

[cwunder]

baexps_pr1 wrote:
Can you please confirm the last question I asked above about XRAM initialization when RSTCON2.CLRC=1 before LBIST execution?

Have you reviewed section 3.1.1.4 Stand-by controller handling during start-up?

The start-up procedure will initialize stand-by controller (SCR) RAMs and trigger SCR boot when the last reset:
• was seen by the device as a cold power-on, AND
• has been triggered by EVR pre-regulator - identified by SCU_RSTSTAT.STBYR=1

Therefore you must clear SCU_RSTSTAT flags before running the LBIST if you are going to keep a LBIST count in this memory.