AURIX™ Forum Discussions

[User9635]

Hello Support,

For AURIX 2G family [TC397/TC387] devices, LBIST runs out of 100MHz back-up clock.
After Power On Reset, if the PLL is enabled at 300MHz and CPU Clock is switched to PLL from default Back-up Clock before LBIST is run, will there be any violation of specification?
In essence, when CPU is running out of 300MHz PLL clock, then if we run LBIST, is that allowed at all?
Or, we must always run LBIST first when the CPU is running out of Back-Up Clock?
Please help me understand the correct sequence.
Best Regards

[cwunder]

I am not support but giving you my opinion.

See section 11.2.3.5 Load Jump Sequencing and Voltage Droop
under
Handling simultaneous load jump requests triggered by Software
This tells you that you must ramp down the PLL (and the other cores/peripherals) to match the current that you would have if running from the 100 MHz back-up clock at startup.

I would think you would want to match the conditions from a current load perspective that would be as if the SSW ran the LBIST.