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AURIX™ Forum Discussions

Level 4
Level 4
50 replies posted 50 questions asked 25 replies posted
Hello Support,
Shown below is a snippet from Aurix 1G datasheet describing Port Pin Reset behavior.
I am unable to find out similarly named section in Aurix 2G datasheet.
Can you please provide me some reference where I can find similar Table for Aurix 2G?
Best Regards
1 Reply
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
In the TC3xx, TRST is pulled up instead of down - so the rest of the note does not apply.

See Table 15 Tool Relevant Device Pins of AURIX™ TC3XX Family on page 76 of AURIXTC3XX_um_part1_v1.5.pdf.

If you're talking about GPIO, see 14.4.2 Port Input/Output Control Registers on page 1262:

When a cold reset is activated and HWCFG6=1, the port pins except P33.8, P40 and P41 are
set to input pull-up mode, P33.8, P40 and P41 are in tri-state mode as long as PORST is activated.If HWCFG6=0,
the pins have the default state of tri-state mode.
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